Commit c911ad22 authored by Arınç ÜNAL's avatar Arınç ÜNAL Committed by Linus Walleij
Browse files

dt-bindings: pinctrl: {mediatek,ralink}: fix formatting 



Change the style of description properties to plain style where there's no
need to preserve the line endings, and vice versa.

Fix capitalisation and indentation.

Fit the schemas to 80 columns for each line.

Signed-off-by: default avatarArınç ÜNAL <arinc.unal@arinc9.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230317213011.13656-16-arinc.unal@arinc9.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent a9d44c4c

Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml

+11 −11
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ title: MediaTek MT65xx Pin Controller 
maintainers:

  - Sean Wang <sean.wang@kernel.org>



description: |+

description:

  The MediaTek's MT65xx Pin controller is used to control SoC pins.



properties:
@@ -30,7 +30,7 @@ properties: 


  pins-are-numbered:

    $ref: /schemas/types.yaml#/definitions/flag

    description: |

    description:

      Specify the subnodes are using numbered pinmux to specify pins. (UNUSED)

    deprecated: true
@@ -38,10 +38,10 @@ properties: 


  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.

    description:

      Number of cells in GPIO specifier. Since the generic GPIO binding is used,

      the amount of cells must be specified as 2. See the below mentioned gpio

      binding representation for description of particular cells.



  mediatek,pctl-regmap:

    $ref: /schemas/types.yaml#/definitions/phandle-array
@@ -49,7 +49,7 @@ properties: 
      maxItems: 1

    minItems: 1

    maxItems: 2

    description: |

    description:

      Should be phandles of the syscfg node.



  interrupt-controller: true
@@ -77,7 +77,7 @@ patternProperties: 
      '(^pins|pins?$)':

        type: object

        additionalProperties: false

        description: |

        description:

          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer
@@ -88,14 +88,14 @@ patternProperties: 
        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in <soc>-pinfunc.h directly.



          bias-disable: true



          bias-pull-up:

            description: |

            description:

              Besides generic pinconfig options, it can be used as the pull up

              settings for 2 pull resistors, R0 and R1. User can configure those

              special pins. Some macros have been defined for this usage, such
@@ -117,7 +117,7 @@ patternProperties: 
          input-schmitt-disable: true



          drive-strength:

            description: |

            description:

              Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,

              etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.

Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

+18 −15
Original line number Diff line number Diff line
@@ -11,8 +11,8 @@ maintainers: 
  - Sean Wang <sean.wang@kernel.org>



description:

  The MediaTek pin controller on MT6779 is used to control pin

  functions, pull up/down resistance and drive strength options.

  The MediaTek pin controller on MT6779 is used to control pin functions, pull

  up/down resistance and drive strength options.



properties:

  compatible:
@@ -29,22 +29,22 @@ properties: 


  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.

    description:

      Number of cells in GPIO specifier. Since the generic GPIO binding is used,

      the amount of cells must be specified as 2. See the below mentioned gpio

      binding representation for description of particular cells.



  gpio-ranges:

    minItems: 1

    maxItems: 5

    description: |

    description:

      GPIO valid number range.



  interrupt-controller: true



  interrupts:

    maxItems: 1

    description: |

    description:

      Specifies the summary IRQ.



  "#interrupt-cells":
@@ -118,19 +118,20 @@ patternProperties: 
    patternProperties:

      '-pins*$':

        type: object

        description: |

        description:

          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and input schmitt.

          configuration, pullups, drive strength, input enable/disable and input

          schmitt.

        $ref: "/schemas/pinctrl/pincfg-node.yaml"



        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are defined

              as macros in boot/dts/<soc>-pinfunc.h directly.

              Integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in boot/dts/<soc>-pinfunc.h directly.



          bias-disable: true
@@ -159,7 +160,8 @@ patternProperties: 
          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              configure those special pins. Valid arguments are described as

              below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
@@ -170,7 +172,8 @@ patternProperties: 
          mediatek,pull-down-adv:

            description: |

              Pull down settings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              configure those special pins. Valid arguments are described as

              below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml

+21 −20
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

  - Sean Wang <sean.wang@kernel.org>



description: |

description:

  The MediaTek's MT6795 Pin controller is used to control SoC pins.



properties:
@@ -20,10 +20,10 @@ properties: 
  gpio-controller: true



  '#gpio-cells':

    description: |

    description:

      Number of cells in GPIO specifier. Since the generic GPIO binding is used,

      the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.

      the amount of cells must be specified as 2. See the below mentioned gpio

      binding representation for description of particular cells.

    const: 2



  gpio-ranges:
@@ -32,7 +32,7 @@ properties: 


  reg:

    description:

      Physical address base for gpio base and eint registers.

      Physical address base for GPIO base and eint registers.

    minItems: 2



  reg-names:
@@ -65,8 +65,8 @@ patternProperties: 
          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and

          input schmitt.

          configuration, pullups, drive strength, input enable/disable and input

          schmitt.

          An example of using macro:

          pincontroller {

            /* GPIO0 set as multifunction GPIO0 */
@@ -86,11 +86,10 @@ patternProperties: 


        properties:

          pinmux:

            description: |

            description:

              Integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are

              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h

              directly.

              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.



          drive-strength:

            enum: [2, 4, 6, 8, 10, 12, 14, 16]
@@ -100,7 +99,7 @@ patternProperties: 
              - type: boolean

              - enum: [100, 101, 102, 103]

                description: mt6795 pull down PUPD/R0/R1 type define value.

            description: |

            description:

              For normal pull down type, it is not necessary to specify R1R0

              values; When pull down type is PUPD/R0/R1, adding R1R0 defines

              will set different resistance values.
@@ -110,10 +109,10 @@ patternProperties: 
              - type: boolean

              - enum: [100, 101, 102, 103]

                description: mt6795 pull up PUPD/R0/R1 type define value.

            description: |

            description:

              For normal pull up type, it is not necessary to specify R1R0

               values; When pull up type is PUPD/R0/R1, adding R1R0 defines

               will set different resistance values.

              values; When pull up type is PUPD/R0/R1, adding R1R0 defines will

              set different resistance values.



          bias-disable: true
@@ -132,7 +131,8 @@ patternProperties: 
          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              configure those special pins. Valid arguments are described as

              below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
@@ -143,7 +143,8 @@ patternProperties: 
          mediatek,pull-down-adv:

            description: |

              Pull down settings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              configure those special pins. Valid arguments are described as

              below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - Arınç ÜNAL <arinc.unal@arinc9.com>

  - Sergio Paracuellos <sergio.paracuellos@gmail.com>



description:

description: |

  MediaTek MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs.

  The pin controller can only set the muxing of pin groups. Muxing individual

  pins is not supported. There is no pinconf support.

Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml

+1 −1
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - Arınç ÜNAL <arinc.unal@arinc9.com>

  - Sergio Paracuellos <sergio.paracuellos@gmail.com>



description:

description: |

  MediaTek MT7621 pin controller for MT7621 SoC.

  The pin controller can only set the muxing of pin groups. Muxing individual

  pins is not supported. There is no pinconf support.