Commit c910b99c authored by Junhao He's avatar Junhao He Committed by Zheng Zengkai
Browse files

coresight: etm4x: Fix accesses to TRCSEQRSTEVR and TRCSEQSTR 

driver inclusion
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I5YCYK



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The TRCSEQRSTEVR and TRCSEQSTR register is not implemented if the
TRCIDR5.NUMSEQSTATE == 0. Skip accessing the register in such cases.

Signed-off-by: default avatarJunhao He <hejunhao3@huawei.com>
Reviewed-by: default avatarLing Mingqiang <lingmingqiang@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent aabaf7d2

drivers/hwtracing/coresight/coresight-etm4x-core.c

+12 −7
Original line number Diff line number Diff line
@@ -428,8 +428,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
		etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);

	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));

	if (drvdata->nrseqstate) {

		etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);

		etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);

	}

	etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);



	for (i = 0; i < drvdata->nr_cntr; i++) {
@@ -1622,9 +1624,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));



	if (drvdata->nrseqstate) {

		state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);



		state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);

	}

	state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);



	for (i = 0; i < drvdata->nr_cntr; i++) {
@@ -1751,8 +1754,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 
	for (i = 0; i < drvdata->nrseqstate - 1; i++)

		etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));



	if (drvdata->nrseqstate) {

		etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);

		etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);

	}

	etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);



	for (i = 0; i < drvdata->nr_cntr; i++) {