Commit c8a0739b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ntb-4.15' of git://github.com/jonmason/ntb 

Pull ntb updates from Jon Mason:
 "Support for the switchtec ntb and related changes. Also, a couple of
  bug fixes"

[ The timing isn't great. I had asked people to send me pull requests
  before my family vacation, and this code has not even been in
  linux-next as far as I can tell. But Logan Gunthorpe pleaded for its
  inclusion because the Switchtec driver has apparently been around for
  a while, just never in linux-next - Linus ]

* tag 'ntb-4.15' of git://github.com/jonmason/ntb:
  ntb: intel: remove b2b memory window workaround for Skylake NTB
  NTB: make idt_89hpes_cfg const
  NTB: switchtec_ntb: Update switchtec documentation with notes for NTB
  NTB: switchtec_ntb: Add memory window support
  NTB: switchtec_ntb: Implement scratchpad registers
  NTB: switchtec_ntb: Implement doorbell registers
  NTB: switchtec_ntb: Add link management
  NTB: switchtec_ntb: Add skeleton NTB driver
  NTB: switchtec_ntb: Initialize hardware for doorbells and messages
  NTB: switchtec_ntb: Initialize hardware for memory windows
  NTB: switchtec_ntb: Introduce initial NTB driver
  NTB: Add check and comment for link up to mw_count() and mw_get_align()
  NTB: Ensure ntb_mw_get_align() is only called when the link is up
  NTB: switchtec: Add link event notifier callback
  NTB: switchtec: Add NTB hardware register definitions
  NTB: switchtec: Export class symbol for use in upper layer driver
  NTB: switchtec: Move structure definitions into a common header
  ntb: update maintainer list for Intel NTB driver
parents 020aae3e 4201a991

Documentation/switchtec.txt

+12 −0
Original line number Original line Diff line number Diff line
@@ -78,3 +78,15 @@ The following IOCTLs are also supported by the device: 
  between PCI Function Framework number (used by the event system)

  between PCI Function Framework number (used by the event system)

  and Switchtec Logic Port ID and Partition number (which is more

  and Switchtec Logic Port ID and Partition number (which is more

  user friendly).

  user friendly).





Non-Transparent Bridge (NTB) Driver

===================================



An NTB driver is provided for the switchtec hardware in switchtec_ntb.

Currently, it only supports switches configured with exactly 2

partitions. It also requires the following configuration settings:



* Both partitions must be able to access each other's GAS spaces.

  Thus, the bits in the GAS Access Vector under Management Settings

  must be set to support this.

MAINTAINERS

+4 −3
Original line number Original line Diff line number Diff line
@@ -9726,12 +9726,11 @@ S: Supported 
F:	drivers/ntb/hw/idt/

F:	drivers/ntb/hw/idt/





NTB INTEL DRIVER

NTB INTEL DRIVER

M:	Jon Mason <jdmason@kudzu.us>

M:	Dave Jiang <dave.jiang@intel.com>

M:	Dave Jiang <dave.jiang@intel.com>

L:	linux-ntb@googlegroups.com

L:	linux-ntb@googlegroups.com

S:	Supported

S:	Supported

W:	https://github.com/jonmason/ntb/wiki

W:	https://github.com/davejiang/linux/wiki

T:	git git://github.com/jonmason/ntb.git

T:	git https://github.com/davejiang/linux.git

F:	drivers/ntb/hw/intel/

F:	drivers/ntb/hw/intel/





NTFS FILESYSTEM

NTFS FILESYSTEM
@@ -10443,6 +10442,8 @@ F: Documentation/switchtec.txt 
F:	Documentation/ABI/testing/sysfs-class-switchtec

F:	Documentation/ABI/testing/sysfs-class-switchtec

F:	drivers/pci/switch/switchtec*

F:	drivers/pci/switch/switchtec*

F:	include/uapi/linux/switchtec_ioctl.h

F:	include/uapi/linux/switchtec_ioctl.h

F:	include/linux/switchtec.h

F:	drivers/ntb/hw/mscc/





PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)

PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)

M:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

M:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

drivers/ntb/hw/Kconfig

+1 −0
Original line number Original line Diff line number Diff line 
source "drivers/ntb/hw/amd/Kconfig"

source "drivers/ntb/hw/amd/Kconfig"

source "drivers/ntb/hw/idt/Kconfig"

source "drivers/ntb/hw/idt/Kconfig"

source "drivers/ntb/hw/intel/Kconfig"

source "drivers/ntb/hw/intel/Kconfig"

source "drivers/ntb/hw/mscc/Kconfig"

drivers/ntb/hw/Makefile

+1 −0
Original line number Original line Diff line number Diff line 
obj-$(CONFIG_NTB_AMD)	+= amd/

obj-$(CONFIG_NTB_AMD)	+= amd/

obj-$(CONFIG_NTB_IDT)	+= idt/

obj-$(CONFIG_NTB_IDT)	+= idt/

obj-$(CONFIG_NTB_INTEL)	+= intel/

obj-$(CONFIG_NTB_INTEL)	+= intel/

obj-$(CONFIG_NTB_SWITCHTEC) += mscc/

drivers/ntb/hw/idt/ntb_hw_idt.c

+8 −8
Original line number Original line Diff line number Diff line
@@ -2628,35 +2628,35 @@ static void idt_pci_remove(struct pci_dev *pdev) 
/*

/*

 * IDT PCIe-switch models ports configuration structures

 * IDT PCIe-switch models ports configuration structures

 */

 */

static struct idt_89hpes_cfg idt_89hpes24nt6ag2_config = {

static const struct idt_89hpes_cfg idt_89hpes24nt6ag2_config = {

	.name = "89HPES24NT6AG2",

	.name = "89HPES24NT6AG2",

	.port_cnt = 6, .ports = {0, 2, 4, 6, 8, 12}

	.port_cnt = 6, .ports = {0, 2, 4, 6, 8, 12}

};

};

static struct idt_89hpes_cfg idt_89hpes32nt8ag2_config = {

static const struct idt_89hpes_cfg idt_89hpes32nt8ag2_config = {

	.name = "89HPES32NT8AG2",

	.name = "89HPES32NT8AG2",

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

};

};

static struct idt_89hpes_cfg idt_89hpes32nt8bg2_config = {

static const struct idt_89hpes_cfg idt_89hpes32nt8bg2_config = {

	.name = "89HPES32NT8BG2",

	.name = "89HPES32NT8BG2",

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

};

};

static struct idt_89hpes_cfg idt_89hpes12nt12g2_config = {

static const struct idt_89hpes_cfg idt_89hpes12nt12g2_config = {

	.name = "89HPES12NT12G2",

	.name = "89HPES12NT12G2",

	.port_cnt = 3, .ports = {0, 8, 16}

	.port_cnt = 3, .ports = {0, 8, 16}

};

};

static struct idt_89hpes_cfg idt_89hpes16nt16g2_config = {

static const struct idt_89hpes_cfg idt_89hpes16nt16g2_config = {

	.name = "89HPES16NT16G2",

	.name = "89HPES16NT16G2",

	.port_cnt = 4, .ports = {0, 8, 12, 16}

	.port_cnt = 4, .ports = {0, 8, 12, 16}

};

};

static struct idt_89hpes_cfg idt_89hpes24nt24g2_config = {

static const struct idt_89hpes_cfg idt_89hpes24nt24g2_config = {

	.name = "89HPES24NT24G2",

	.name = "89HPES24NT24G2",

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

};

};

static struct idt_89hpes_cfg idt_89hpes32nt24ag2_config = {

static const struct idt_89hpes_cfg idt_89hpes32nt24ag2_config = {

	.name = "89HPES32NT24AG2",

	.name = "89HPES32NT24AG2",

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

};

};

static struct idt_89hpes_cfg idt_89hpes32nt24bg2_config = {

static const struct idt_89hpes_cfg idt_89hpes32nt24bg2_config = {

	.name = "89HPES32NT24BG2",

	.name = "89HPES32NT24BG2",

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

	.port_cnt = 8, .ports = {0, 2, 4, 6, 8, 12, 16, 20}

};

};