Commit c8754c51 authored by Frederic Barrat's avatar Frederic Barrat Committed by Michael Ellerman
Browse files

powerpc/pseries: Define PCI bus speed for Gen4 and Gen5



Update bus speed definition for PCI Gen4 and 5.

Signed-off-by: default avatarFrederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201130152949.26467-1-fbarrat@linux.ibm.com
parent 1baa1f70
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+21 −30
Original line number Diff line number Diff line
@@ -290,6 +290,25 @@ static void fixup_winbond_82c105(struct pci_dev* dev)
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
			 fixup_winbond_82c105);

static enum pci_bus_speed prop_to_pci_speed(u32 prop)
{
	switch (prop) {
	case 0x01:
		return PCIE_SPEED_2_5GT;
	case 0x02:
		return PCIE_SPEED_5_0GT;
	case 0x04:
		return PCIE_SPEED_8_0GT;
	case 0x08:
		return PCIE_SPEED_16_0GT;
	case 0x10:
		return PCIE_SPEED_32_0GT;
	default:
		pr_debug("Unexpected PCI link speed property value\n");
		return PCI_SPEED_UNKNOWN;
	}
}

int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
{
	struct device_node *dn, *pdn;
@@ -322,35 +341,7 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
		return 0;
	}

	switch (pcie_link_speed_stats[0]) {
	case 0x01:
		bus->max_bus_speed = PCIE_SPEED_2_5GT;
		break;
	case 0x02:
		bus->max_bus_speed = PCIE_SPEED_5_0GT;
		break;
	case 0x04:
		bus->max_bus_speed = PCIE_SPEED_8_0GT;
		break;
	default:
		bus->max_bus_speed = PCI_SPEED_UNKNOWN;
		break;
	}

	switch (pcie_link_speed_stats[1]) {
	case 0x01:
		bus->cur_bus_speed = PCIE_SPEED_2_5GT;
		break;
	case 0x02:
		bus->cur_bus_speed = PCIE_SPEED_5_0GT;
		break;
	case 0x04:
		bus->cur_bus_speed = PCIE_SPEED_8_0GT;
		break;
	default:
		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
		break;
	}

	bus->max_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[0]);
	bus->cur_bus_speed = prop_to_pci_speed(pcie_link_speed_stats[1]);
	return 0;
}