Unverified Commit c872138c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'aspeed-5.15-devicetree' of... 

Merge tag 'aspeed-5.15-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt

ASPEED device tree updates for 5.15

 - New machines

  * Facebook's Cloudripper
  * Facebook's Elbert
  * Facebook's Fuji

  All three carry the description of "Facebook's next generation switch
  platform with an AST2600 BMC integrated for health monitoring
  purpose."

  They share a 128 MB SPI NOR flash layout that is also used by some
  older platforms.

  * Inspur's NF5280M6, an x86 platform server with an AST2500-based BMC

 - SGPIO updates including AST2600 support

 - GPIO descriptions for the IBM AST2600 machines

 - Pinctrl fix

 - Updates to Facebook's AST2500 based machines

* tag 'aspeed-5.15-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: (23 commits)
  ARM: dts: aspeed: p10bmc: Add power control pins
  ARM: dts: aspeed: cloudripper: Add comments for "mdio1"
  ARM: dts: aspeed: minipack: Update flash partition table
  ARM: dts: aspeed: Add Facebook Fuji (AST2600) BMC
  ARM: dts: aspeed: Add Facebook Elbert (AST2600) BMC
  ARM: dts: aspeed: Add Facebook Cloudripper (AST2600) BMC
  ARM: dts: aspeed: Common dtsi for Facebook AST2600 Network BMCs
  ARM: dts: aspeed: wedge400: Use common flash layout
  ARM: dts: Add Facebook BMC 128MB flash layout
  ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
  ARM: dts: aspeed-g6: Add SGPIO node.
  dt-bindings: aspeed-sgpio: Add ast2600 sgpio
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  ARM: dts: aspeed: ast2500evb: Enable built in RTC
  ARM: dts: aspeed: tacoma: Add TPM reset GPIO
  ARM: dts: rainier, everest: Add TPM reset GPIO
  ARM: dts: aspeed: wedge100: Enable ADC channels
  ARM: dts: aspeed: galaxy100: Remove redundant ADC device
  ARM: dts: aspeed: wedge40: Remove redundant ADC device
  ARM: dts: aspeed: Enable ADC in Facebook AST2400 common dtsi
  ...

Link: https://lore.kernel.org/r/CACPK8XdWRBb9cuDWGQPfK8R8TsZuydJQHsL4_e2w=HvCKAMogg@mail.gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a0f480dc 6b8b3126

Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Aspeed SGPIO controller



maintainers:

  - Andrew Jeffery <andrew@aj.id.au>



description:

  This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,

  AST2600 have two sgpio master one with 128 pins another one with 80 pins,

  AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial

  GPIO pins can be programmed to support the following options

  - Support interrupt option for each input port and various interrupt

    sensitivity option (level-high, level-low, edge-high, edge-low)

  - Support reset tolerance option for each output port

  - Directly connected to APB bus and its shift clock is from APB bus clock

    divided by a programmable value.

  - Co-work with external signal-chained TTL components (74LV165/74LV595)



properties:

  compatible:

    enum:

      - aspeed,ast2400-sgpio

      - aspeed,ast2500-sgpio

      - aspeed,ast2600-sgpiom



  reg:

    maxItems: 1



  gpio-controller: true



  '#gpio-cells':

    const: 2



  interrupts:

    maxItems: 1



  interrupt-controller: true



  clocks:

    maxItems: 1



  ngpios: true



  bus-frequency: true



required:

  - compatible

  - reg

  - gpio-controller

  - '#gpio-cells'

  - interrupts

  - interrupt-controller

  - ngpios

  - clocks

  - bus-frequency



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/aspeed-clock.h>

    sgpio: sgpio@1e780200 {

        #gpio-cells = <2>;

        compatible = "aspeed,ast2500-sgpio";

        gpio-controller;

        interrupts = <40>;

        reg = <0x1e780200 0x0100>;

        clocks = <&syscon ASPEED_CLK_APB>;

        interrupt-controller;

        ngpios = <80>;

        bus-frequency = <12000000>;

    };

Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

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Aspeed SGPIO controller Device Tree Bindings

--------------------------------------------



This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full

featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to

support the following options:

- Support interrupt option for each input port and various interrupt

  sensitivity option (level-high, level-low, edge-high, edge-low)

- Support reset tolerance option for each output port

- Directly connected to APB bus and its shift clock is from APB bus clock

  divided by a programmable value.

- Co-work with external signal-chained TTL components (74LV165/74LV595)



Required properties:



- compatible : Should be one of

  "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"

- #gpio-cells : Should be 2, see gpio.txt

- reg : Address and length of the register set for the device

- gpio-controller : Marks the device node as a GPIO controller

- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt

- interrupt-controller : Mark the GPIO controller as an interrupt-controller

- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose

  2 software GPIOs per hardware GPIO: one for hardware input, one for hardware

  output. Up to 80 pins, must be a multiple of 8.

- clocks : A phandle to the APB clock for SGPM clock division

- bus-frequency : SGPM CLK frequency



The sgpio and interrupt properties are further described in their respective

bindings documentation:



- Documentation/devicetree/bindings/gpio/gpio.txt

- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt



  Example:

	sgpio: sgpio@1e780200 {

		#gpio-cells = <2>;

		compatible = "aspeed,ast2500-sgpio";

		gpio-controller;

		interrupts = <40>;

		reg = <0x1e780200 0x0100>;

		clocks = <&syscon ASPEED_CLK_APB>;

		interrupt-controller;

		ngpios = <8>;

		bus-frequency = <12000000>;

	};

arch/arm/boot/dts/Makefile

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@@ -1462,7 +1462,10 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ 
	aspeed-bmc-arm-stardragon4800-rep2.dtb \

	aspeed-bmc-asrock-e3c246d4i.dtb \

	aspeed-bmc-bytedance-g220a.dtb \

	aspeed-bmc-facebook-cloudripper.dtb \

	aspeed-bmc-facebook-cmm.dtb \

	aspeed-bmc-facebook-elbert.dtb \

	aspeed-bmc-facebook-fuji.dtb \

	aspeed-bmc-facebook-galaxy100.dtb \

	aspeed-bmc-facebook-minipack.dtb \

	aspeed-bmc-facebook-tiogapass.dtb \
@@ -1477,6 +1480,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ 
	aspeed-bmc-ibm-rainier-4u.dtb \

	aspeed-bmc-intel-s2600wf.dtb \

	aspeed-bmc-inspur-fp5280g2.dtb \

	aspeed-bmc-inspur-nf5280m6.dtb \

	aspeed-bmc-lenovo-hr630.dtb \

	aspeed-bmc-lenovo-hr855xg2.dtb \

	aspeed-bmc-microsoft-olympus.dtb \

arch/arm/boot/dts/aspeed-ast2500-evb.dts

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@@ -129,3 +129,7 @@ 
     status = "okay";

     memory-region = <&gfx_memory>;

};



&rtc {

	status = "okay";

};

arch/arm/boot/dts/aspeed-bmc-facebook-cloudripper.dts

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// SPDX-License-Identifier: GPL-2.0+

// Copyright (c) 2020 Facebook Inc.



/dts-v1/;



#include <dt-bindings/leds/common.h>

#include "ast2600-facebook-netbmc-common.dtsi"



/ {

	model = "Facebook Cloudripper BMC";

	compatible = "facebook,cloudripper-bmc", "aspeed,ast2600";



	aliases {

		/*

		 * PCA9548 (1-0070) provides 8 channels connecting to

		 * SMB (Switch Main Board).

		 */

		i2c16 = &imux16;

		i2c17 = &imux17;

		i2c18 = &imux18;

		i2c19 = &imux19;

		i2c20 = &imux20;

		i2c21 = &imux21;

		i2c22 = &imux22;

		i2c23 = &imux23;



		/*

		 * PCA9548 (2-0070) provides 8 channels connecting to

		 * SCM (System Controller Module).

		 */

		i2c24 = &imux24;

		i2c25 = &imux25;

		i2c26 = &imux26;

		i2c27 = &imux27;

		i2c28 = &imux28;

		i2c29 = &imux29;

		i2c30 = &imux30;

		i2c31 = &imux31;



		/*

		 * PCA9548 (3-0070) provides 8 channels connecting to

		 * SMB (Switch Main Board).

		 */

		i2c32 = &imux32;

		i2c33 = &imux33;

		i2c34 = &imux34;

		i2c35 = &imux35;

		i2c36 = &imux36;

		i2c37 = &imux37;

		i2c38 = &imux38;

		i2c39 = &imux39;



		/*

		 * PCA9548 (8-0070) provides 8 channels connecting to

		 * PDB (Power Delivery Board).

		 */

		i2c40 = &imux40;

		i2c41 = &imux41;

		i2c42 = &imux42;

		i2c43 = &imux43;

		i2c44 = &imux44;

		i2c45 = &imux45;

		i2c46 = &imux46;

		i2c47 = &imux47;



		/*

		 * PCA9548 (15-0076) provides 8 channels connecting to

		 * FCM (Fan Controller Module).

		 */

		i2c48 = &imux48;

		i2c49 = &imux49;

		i2c50 = &imux50;

		i2c51 = &imux51;

		i2c52 = &imux52;

		i2c53 = &imux53;

		i2c54 = &imux54;

		i2c55 = &imux55;

	};



	spi_gpio: spi-gpio {

		num-chipselects = <2>;

		cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>,

			   <&gpio0 ASPEED_GPIO(X, 1) GPIO_ACTIVE_HIGH>;



		eeprom@1 {

			compatible = "atmel,at93c46d";

			spi-max-frequency = <250000>;

			data-size = <16>;

			spi-cs-high;

			reg = <1>;

		};

	};

};



&ehci1 {

	status = "okay";

};



/*

 * "mdio1" is connected to the MDC/MDIO interface of the on-board

 * management switch (whose ports are connected to BMC, Host and front

 * panel ethernet port).

 */

&mdio1 {

	status = "okay";

};



&mdio3 {

	status = "okay";



	ethphy1: ethernet-phy@13 {

		compatible = "ethernet-phy-ieee802.3-c22";

		reg = <0x0d>;

	};

};



&mac3 {

	status = "okay";

	phy-mode = "rgmii";

	phy-handle = <&ethphy1>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_rgmii4_default>;

};



&i2c0 {

	multi-master;

	bus-frequency = <1000000>;

};



&i2c1 {

	/*

	 * PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch

	 * Main Board).

	 */

	i2c-switch@70 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		imux16: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

		};



		imux17: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

		};



		imux18: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

		};



		imux19: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

		};



		imux20: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <4>;

		};



		imux21: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <5>;

		};



		imux22: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <6>;

		};



		imux23: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <7>;

		};

	};

};



&i2c2 {

	/*

	 * PCA9548 (2-0070) provides 8 channels connecting to SCM (System

	 * Controller Module).

	 */

	i2c-switch@70 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		imux24: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

		};



		imux25: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

		};



		imux26: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

		};



		imux27: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

		};



		imux28: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <4>;

		};



		imux29: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <5>;

		};



		imux30: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <6>;

		};



		imux31: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <7>;

		};

	};

};



&i2c3 {

	/*

	 * PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch

	 * Main Board).

	 */

	i2c-switch@70 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		imux32: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

		};



		imux33: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

		};



		imux34: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

		};



		imux35: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

		};



		imux36: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <4>;

		};



		imux37: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <5>;

		};



		imux38: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <6>;

		};



		imux39: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <7>;

		};

	};

};



&i2c6 {

	lp5012@14 {

		compatible = "ti,lp5012";

		reg = <0x14>;

		#address-cells = <1>;

		#size-cells = <0>;



		multi-led@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

			color = <LED_COLOR_ID_MULTI>;

			function = LED_FUNCTION_ACTIVITY;

			label = "sys";



			led@0 {

				reg = <0>;

				color = <LED_COLOR_ID_RED>;

			};



			led@1 {

				reg = <1>;

				color = <LED_COLOR_ID_BLUE>;

			};



			led@2 {

				reg = <2>;

				color = <LED_COLOR_ID_GREEN>;

			};

		};



		multi-led@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

			color = <LED_COLOR_ID_MULTI>;

			function = LED_FUNCTION_ACTIVITY;

			label = "fan";



			led@0 {

				reg = <0>;

				color = <LED_COLOR_ID_RED>;

			};



			led@1 {

				reg = <1>;

				color = <LED_COLOR_ID_BLUE>;

			};



			led@2 {

				reg = <2>;

				color = <LED_COLOR_ID_GREEN>;

			};

		};



		multi-led@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

			color = <LED_COLOR_ID_MULTI>;

			function = LED_FUNCTION_ACTIVITY;

			label = "psu";



			led@0 {

				reg = <0>;

				color = <LED_COLOR_ID_RED>;

			};



			led@1 {

				reg = <1>;

				color = <LED_COLOR_ID_BLUE>;

			};



			led@2 {

				reg = <2>;

				color = <LED_COLOR_ID_GREEN>;

			};

		};



		multi-led@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

			color = <LED_COLOR_ID_MULTI>;

			function = LED_FUNCTION_ACTIVITY;

			label = "scm";



			led@0 {

				reg = <0>;

				color = <LED_COLOR_ID_RED>;

			};



			led@1 {

				reg = <1>;

				color = <LED_COLOR_ID_BLUE>;

			};



			led@2 {

				reg = <2>;

				color = <LED_COLOR_ID_GREEN>;

			};

		};

	};

};



&i2c8 {

	/*

	 * PCA9548 (8-0070) provides 8 channels connecting to PDB (Power

	 * Delivery Board).

	 */

	i2c-switch@70 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		imux40: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

		};



		imux41: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

		};



		imux42: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

		};



		imux43: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

		};



		imux44: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <4>;

		};



		imux45: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <5>;

		};



		imux46: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <6>;

		};



		imux47: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <7>;

		};



	};

};



&i2c15 {

	/*

	 * PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan

	 * Controller Module).

	 */

	i2c-switch@76 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x76>;

		i2c-mux-idle-disconnect;



		imux48: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0>;

		};



		imux49: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <1>;

		};



		imux50: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <2>;

		};



		imux51: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <3>;

		};



		imux52: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <4>;

		};



		imux53: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <5>;

		};



		imux54: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <6>;

		};



		imux55: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <7>;

		};

	};

};