clk: qcom: gcc-sm8250: use ARRAY_SIZE instead of specifying num_parents (c864cd5f) · Commits · EulixOS / Software / Kernel

drivers/clk/qcom/gcc-sm8250.c

+46 −46

Original line number	Diff line number	Diff line
		@@ -199,7 +199,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_cpuss_ahb_clk_src",
		.parent_data = gcc_parent_data_0_ao,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_rcg2_ops,
		},
		@@ -223,7 +223,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp1_clk_src",
		.parent_data = gcc_parent_data_1,
		.num_parents = 4,
		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -237,7 +237,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp2_clk_src",
		.parent_data = gcc_parent_data_1,
		.num_parents = 4,
		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -251,7 +251,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_gp3_clk_src",
		.parent_data = gcc_parent_data_1,
		.num_parents = 4,
		.num_parents = ARRAY_SIZE(gcc_parent_data_1),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -271,7 +271,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_0_aux_clk_src",
		.parent_data = gcc_parent_data_2,
		.num_parents = 2,
		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -285,7 +285,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_1_aux_clk_src",
		.parent_data = gcc_parent_data_2,
		.num_parents = 2,
		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -299,7 +299,7 @@ static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_2_aux_clk_src",
		.parent_data = gcc_parent_data_2,
		.num_parents = 2,
		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -319,7 +319,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pcie_phy_refgen_clk_src",
		.parent_data = gcc_parent_data_0_ao,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -340,7 +340,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_pdm2_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -368,7 +368,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
		static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s0_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -384,7 +384,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s1_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -416,7 +416,7 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
		static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s2_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -432,7 +432,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s3_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -448,7 +448,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s4_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -464,7 +464,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s5_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -480,7 +480,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s6_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -496,7 +496,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
		.name = "gcc_qupv3_wrap0_s7_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -512,7 +512,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s0_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -528,7 +528,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s1_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -544,7 +544,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s2_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -560,7 +560,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s3_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -576,7 +576,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s4_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -592,7 +592,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
		.name = "gcc_qupv3_wrap1_s5_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -608,7 +608,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s0_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -624,7 +624,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s1_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -640,7 +640,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s2_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s3_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -672,7 +672,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s4_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -688,7 +688,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
		static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
		.name = "gcc_qupv3_wrap2_s5_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		};

		@@ -720,7 +720,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_sdcc2_apps_clk_src",
		.parent_data = gcc_parent_data_4,
		.num_parents = 5,
		.num_parents = ARRAY_SIZE(gcc_parent_data_4),
		.ops = &clk_rcg2_floor_ops,
		},
		};
		@@ -743,7 +743,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_sdcc4_apps_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_floor_ops,
		},
		};
		@@ -762,7 +762,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_tsif_ref_clk_src",
		.parent_data = gcc_parent_data_5,
		.num_parents = 4,
		.num_parents = ARRAY_SIZE(gcc_parent_data_5),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -784,7 +784,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_card_axi_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -806,7 +806,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_card_ice_core_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -825,7 +825,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_card_phy_aux_clk_src",
		.parent_data = gcc_parent_data_3,
		.num_parents = 1,
		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -846,7 +846,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_card_unipro_core_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -869,7 +869,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_phy_axi_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -883,7 +883,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_phy_ice_core_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -897,7 +897,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_phy_phy_aux_clk_src",
		.parent_data = gcc_parent_data_3,
		.num_parents = 1,
		.num_parents = ARRAY_SIZE(gcc_parent_data_3),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -911,7 +911,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_phy_unipro_core_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -934,7 +934,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_prim_master_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -948,7 +948,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_prim_mock_utmi_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -962,7 +962,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_sec_master_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -976,7 +976,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb30_sec_mock_utmi_clk_src",
		.parent_data = gcc_parent_data_0,
		.num_parents = 3,
		.num_parents = ARRAY_SIZE(gcc_parent_data_0),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -990,7 +990,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_prim_phy_aux_clk_src",
		.parent_data = gcc_parent_data_2,
		.num_parents = 2,
		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
		.ops = &clk_rcg2_ops,
		},
		};
		@@ -1004,7 +1004,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_usb3_sec_phy_aux_clk_src",
		.parent_data = gcc_parent_data_2,
		.num_parents = 2,
		.num_parents = ARRAY_SIZE(gcc_parent_data_2),
		.ops = &clk_rcg2_ops,
		},
		};