Commit c84ff24a authored by Robin Chen's avatar Robin Chen Committed by Alex Deucher
Browse files

drm/amd/display: Pass DSC slice height to PSR FW 



[Why]
When DSC is enabled, the PSRSU seletive update region
must be multiple number of DSC slice height number.
The original solution is to overwrite the SU Y granularity
by DSC slice height in DAL driver. However, the size
of the SU Y granularity variable only has 8 bytes
and the DSC slice height may over the 8 bytes size.

[How]
Instead of overwriting the SU Y granularity value,
add a new DSC slice height pararmeter and pass it
to DMUB PSRSU FW. The PSRSU FW will refer to the
DSC slice height value and extend the SU region.

Reviewed-by: default avatarDennis Chan <dennis.chan@amd.com>
Reviewed-by: default avatarChunTao Tso <chuntao.tso@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarRobin Chen <robin.chen@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ca7415f

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

+1 −1
Original line number Diff line number Diff line
@@ -122,7 +122,7 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream) 
		psr_config.allow_multi_disp_optimizations =

			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);



		if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))

		if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))

			return false;



		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);

drivers/gpu/drm/amd/display/dc/dc_types.h

+2 −0
Original line number Diff line number Diff line
@@ -691,6 +691,7 @@ struct psr_config { 
	uint8_t su_y_granularity;

	unsigned int line_time_in_us;

	uint8_t rate_control_caps;

	uint16_t dsc_slice_height;

};



union dmcu_psr_level {
@@ -802,6 +803,7 @@ struct psr_context { 
	uint8_t su_y_granularity;

	unsigned int line_time_in_us;

	uint8_t rate_control_caps;

	uint16_t dsc_slice_height;

};



struct colorspace_transform {

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

+1 −0
Original line number Diff line number Diff line
@@ -417,6 +417,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, 
	copy_settings_data->relock_delay_frame_cnt = 0;

	if (link->dpcd_caps.sink_dev_id == DP_BRANCH_DEVICE_ID_001CF8)

		copy_settings_data->relock_delay_frame_cnt = 2;

	copy_settings_data->dsc_slice_height = psr_context->dsc_slice_height;



	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);

	dc_dmub_srv_cmd_execute(dc->dmub_srv);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

+2 −0
Original line number Diff line number Diff line
@@ -736,6 +736,8 @@ bool dc_link_setup_psr(struct dc_link *link, 
	 */

	psr_context->frame_delay = 0;



	psr_context->dsc_slice_height = psr_config->dsc_slice_height;



	if (psr) {

		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,

			link, psr_context, panel_inst);

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+8 −0
Original line number Diff line number Diff line
@@ -1968,6 +1968,14 @@ struct dmub_cmd_psr_copy_settings_data { 
	 * Explicit padding to 2 byte boundary.

	 */

	uint8_t pad3;

	/**

	 * DSC Slice height.

	 */

	uint16_t dsc_slice_height;

	/**

	 * Explicit padding to 4 byte boundary.

	 */

	uint16_t pad;

};



/**