Commit c83bc86a authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'Renesas-rz-n1' 

Clément Léger says:

====================
net: add support for Renesas RZ/N1 ethernet su

The Renesas RZ/N1 SoCs features an ethernet subsystem which contains
(most notably) a switch, two GMACs, and a MII converter [1]. This
series adds support for the switch and the MII converter.

The MII converter present on this SoC has been represented as a PCS
which sit between the MACs and the PHY. This PCS driver is probed from
the device-tree since it requires to be configured. Indeed the MII
converter also contains the registers that are handling the muxing of
ports (Switch, MAC, HSR, RTOS, etc) internally to the SoC.

The switch driver is based on DSA and exposes 4 ports + 1 CPU
management port. It include basic bridging support as well as FDB and
statistics support.

Link: [1] https://www.renesas.com/us/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals



-----
Changes in V9:
- Cover letter:
  - Remove comment about RZN1 patches that are now in the master branch.
- Commits:
  - Add Vladimir Oltean Reviewed-by
- PCS:
  - Add "Depends on OF" for PCS_RZN1_MIIC due to error found by intel
    kernel test robot <lkp@intel.com>.
  - Check return value of of_property_read_u32() for
    "renesas,miic-switch-portin" property before setting conf.
  - Return miic_parse_dt() return value in miic_probe() on error
- Switch:
  - Add "Depends on OF" for NET_DSA_RZN1_A5PSW due to errors found by
    intel kernel test robot <lkp@intel.com>.
- DT:
  - Add spaces between switch port and '{'
====================

Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ebeae54d 717a5c56

Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/N1 Advanced 5 ports ethernet switch



maintainers:

  - Clément Léger <clement.leger@bootlin.com>



description: |

  The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and

  handles 4 ports + 1 CPU management port.



allOf:

  - $ref: dsa.yaml#



properties:

  compatible:

    items:

      - enum:

          - renesas,r9a06g032-a5psw

      - const: renesas,rzn1-a5psw



  reg:

    maxItems: 1



  power-domains:

    maxItems: 1



  mdio:

    $ref: /schemas/net/mdio.yaml#

    unevaluatedProperties: false



  clocks:

    items:

      - description: AHB clock used for the switch register interface

      - description: Switch system clock



  clock-names:

    items:

      - const: hclk

      - const: clk



  ethernet-ports:

    type: object

    properties:

      '#address-cells':

        const: 1

      '#size-cells':

        const: 0



    patternProperties:

      "^(ethernet-)?port@[0-4]$":

        type: object

        description: Ethernet switch ports



        properties:

          pcs-handle:

            description:

              phandle pointing to a PCS sub-node compatible with

              renesas,rzn1-miic.yaml#

            $ref: /schemas/types.yaml#/definitions/phandle



unevaluatedProperties: false



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - power-domains



examples:

  - |

    #include <dt-bindings/gpio/gpio.h>

    #include <dt-bindings/clock/r9a06g032-sysctrl.h>



    switch@44050000 {

        compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";

        reg = <0x44050000 0x10000>;

        clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>;

        clock-names = "hclk", "clk";

        power-domains = <&sysctrl>;



        dsa,member = <0 0>;



        ethernet-ports {

            #address-cells = <1>;

            #size-cells = <0>;



            port@0 {

                reg = <0>;

                label = "lan0";

                phy-handle = <&switch0phy3>;

                pcs-handle = <&mii_conv4>;

            };



            port@1 {

                reg = <1>;

                label = "lan1";

                phy-handle = <&switch0phy1>;

                pcs-handle = <&mii_conv3>;

            };



            port@4 {

                reg = <4>;

                ethernet = <&gmac2>;

                label = "cpu";

                fixed-link {

                  speed = <1000>;

                  full-duplex;

                };

            };

        };



        mdio {

            #address-cells = <1>;

            #size-cells = <0>;



            reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>;

            reset-delay-us = <15>;

            clock-frequency = <2500000>;



            switch0phy1: ethernet-phy@1{

                reg = <1>;

            };



            switch0phy3: ethernet-phy@3{

                reg = <3>;

            };

        };

    };

Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas RZ/N1 MII converter



maintainers:

  - Clément Léger <clement.leger@bootlin.com>



description: |

  This MII converter is present on the Renesas RZ/N1 SoC family. It is

  responsible to do MII passthrough or convert it to RMII/RGMII.



properties:

  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



  compatible:

    items:

      - enum:

          - renesas,r9a06g032-miic

      - const: renesas,rzn1-miic



  reg:

    maxItems: 1



  clocks:

    items:

      - description: MII reference clock

      - description: RGMII reference clock

      - description: RMII reference clock

      - description: AHB clock used for the MII converter register interface



  clock-names:

    items:

      - const: mii_ref

      - const: rgmii_ref

      - const: rmii_ref

      - const: hclk



  renesas,miic-switch-portin:

    description: MII Switch PORTIN configuration. This value should use one of

      the values defined in dt-bindings/net/pcs-rzn1-miic.h.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [1, 2]



  power-domains:

    maxItems: 1



patternProperties:

  "^mii-conv@[0-5]$":

    type: object

    description: MII converter port



    properties:

      reg:

        description: MII Converter port number.

        enum: [1, 2, 3, 4, 5]



      renesas,miic-input:

        description: Converter input port configuration. This value should use

          one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.

        $ref: /schemas/types.yaml#/definitions/uint32



    required:

      - reg

      - renesas,miic-input



    additionalProperties: false



    allOf:

      - if:

          properties:

            reg:

              const: 1

        then:

          properties:

            renesas,miic-input:

              const: 0

      - if:

          properties:

            reg:

              const: 2

        then:

          properties:

            renesas,miic-input:

              enum: [1, 11]

      - if:

          properties:

            reg:

              const: 3

        then:

          properties:

            renesas,miic-input:

              enum: [7, 10]

      - if:

          properties:

            reg:

              const: 4

        then:

          properties:

            renesas,miic-input:

              enum: [4, 6, 9, 13]

      - if:

          properties:

            reg:

              const: 5

        then:

          properties:

            renesas,miic-input:

              enum: [3, 5, 8, 12]



required:

  - '#address-cells'

  - '#size-cells'

  - compatible

  - reg

  - clocks

  - clock-names

  - power-domains



additionalProperties: false



examples:

  - |

    #include <dt-bindings/net/pcs-rzn1-miic.h>

    #include <dt-bindings/clock/r9a06g032-sysctrl.h>



    eth-miic@44030000 {

      #address-cells = <1>;

      #size-cells = <0>;

      compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";

      reg = <0x44030000 0x10000>;

      clocks = <&sysctrl R9A06G032_CLK_MII_REF>,

              <&sysctrl R9A06G032_CLK_RGMII_REF>,

              <&sysctrl R9A06G032_CLK_RMII_REF>,

              <&sysctrl R9A06G032_HCLK_SWITCH_RG>;

      clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";

      renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;

      power-domains = <&sysctrl>;



      mii_conv1: mii-conv@1 {

        renesas,miic-input = <MIIC_GMAC1_PORT>;

        reg = <1>;

      };



      mii_conv2: mii-conv@2 {

        renesas,miic-input = <MIIC_SWITCH_PORTD>;

        reg = <2>;

      };



      mii_conv3: mii-conv@3 {

        renesas,miic-input = <MIIC_SWITCH_PORTC>;

        reg = <3>;

      };



      mii_conv4: mii-conv@4 {

        renesas,miic-input = <MIIC_SWITCH_PORTB>;

        reg = <4>;

      };



      mii_conv5: mii-conv@5 {

        renesas,miic-input = <MIIC_SWITCH_PORTA>;

        reg = <5>;

      };

    };

Documentation/devicetree/bindings/net/snps,dwmac.yaml

+5 −0
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ properties: 
        - ingenic,x2000-mac

        - loongson,ls2k-dwmac

        - loongson,ls7a-dwmac

        - renesas,r9a06g032-gmac

        - renesas,rzn1-gmac

        - rockchip,px30-gmac

        - rockchip,rk3128-gmac

        - rockchip,rk3228-gmac
@@ -135,6 +137,9 @@ properties: 
  reset-names:

    const: stmmaceth



  power-domains:

    maxItems: 1



  mac-mode:

    $ref: ethernet-controller.yaml#/properties/phy-connection-type

    description:

MAINTAINERS

+13 −0
Original line number Diff line number Diff line
@@ -17056,6 +17056,19 @@ S: Supported 
F:	Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml

F:	drivers/iio/adc/rzg2l_adc.c









RENESAS RZ/N1 A5PSW SWITCH DRIVER









M:	Clément Léger <clement.leger@bootlin.com>









L:	linux-renesas-soc@vger.kernel.org









L:	netdev@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml









F:	Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml









F:	drivers/net/dsa/rzn1_a5psw*









F:	drivers/net/pcs/pcs-rzn1-miic.c









F:	include/dt-bindings/net/pcs-rzn1-miic.h









F:	include/linux/pcs-rzn1-miic.h









F:	net/dsa/tag_rzn1_a5psw.c

















RENESAS RZ/N1 RTC CONTROLLER DRIVER









M:	Miquel Raynal <miquel.raynal@bootlin.com>









L:	linux-rtc@vger.kernel.org
































arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts



+117
−0






























Original line number
Diff line number
Diff line







@@ -8,6 +8,8 @@

















/dts-v1/;



















#include <dt-bindings/pinctrl/rzn1-pinctrl.h>









#include <dt-bindings/net/pcs-rzn1-miic.h>









#include "r9a06g032.dtsi"



















/ {








@@ -31,3 +33,118 @@







	timeout-sec = <60>;









	status = "okay";









};



















&gmac2 {









	status = "okay";









	phy-mode = "gmii";









	fixed-link {









		speed = <1000>;









		full-duplex;









	};









};



















&switch {









	status = "okay";









	#address-cells = <1>;









	#size-cells = <0>;



















	pinctrl-names = "default";









	pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>;



















	dsa,member = <0 0>;



















	mdio {









		clock-frequency = <2500000>;



















		#address-cells = <1>;









		#size-cells = <0>;



















		switch0phy4: ethernet-phy@4 {









			reg = <4>;









			micrel,led-mode = <1>;









		};



















		switch0phy5: ethernet-phy@5 {









			reg = <5>;









			micrel,led-mode = <1>;









		};









	};









};



















&switch_port0 {









	label = "lan0";









	phy-mode = "mii";









	phy-handle = <&switch0phy5>;









	status = "okay";









};



















&switch_port1 {









	label = "lan1";









	phy-mode = "mii";









	phy-handle = <&switch0phy4>;









	status = "okay";









};



















&switch_port4 {









	status = "okay";









};



















&eth_miic {









	status = "okay";









	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;









};



















&mii_conv4 {









	renesas,miic-input = <MIIC_SWITCH_PORTB>;









	status = "okay";









};



















&mii_conv5 {









	renesas,miic-input = <MIIC_SWITCH_PORTA>;









	status = "okay";









};



















&pinctrl{









	pins_mdio1: pins_mdio1 {









		pinmux = <









			RZN1_PINMUX(152, RZN1_FUNC_MDIO1_SWITCH)









			RZN1_PINMUX(153, RZN1_FUNC_MDIO1_SWITCH)









		>;









	};









	pins_eth3: pins_eth3 {









		pinmux = <









			RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









		>;









		drive-strength = <6>;









		bias-disable;









	};









	pins_eth4: pins_eth4 {









		pinmux = <









			RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









			RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)









		>;









		drive-strength = <6>;









		bias-disable;









	};









};