Unverified Commit c836d9d1 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Some Svpbmt fixes

Some additionals comments and notes from autobuilders received after the
series got applied, warranted some changes.

* commit '924cbb8c':
  riscv: Improve description for RISCV_ISA_SVPBMT Kconfig symbol
  riscv: drop cpufeature_apply_feature tracking variable
  riscv: fix dependency for t-head errata
parents a7c1c97f 924cbb8c
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+7 −2
Original line number Diff line number Diff line
@@ -364,8 +364,13 @@ config RISCV_ISA_SVPBMT
	select RISCV_ALTERNATIVE
	default y
	help
	   Adds support to dynamically detect the presence of the SVPBMT extension
	   (Supervisor-mode: page-based memory types) and enable its usage.
	   Adds support to dynamically detect the presence of the SVPBMT
	   ISA-extension (Supervisor-mode: page-based memory types) and
	   enable its usage.

	   The memory type for a page contains a combination of attributes
	   that indicate the cacheability, idempotency, and ordering
	   properties for access to that page.

	   The SVPBMT extension is only available on 64Bit cpus.

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ config ERRATA_SIFIVE_CIP_1200

config ERRATA_THEAD
	bool "T-HEAD errata"
	depends on !XIP_KERNEL
	select RISCV_ALTERNATIVE
	help
	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling
+1 −4
Original line number Diff line number Diff line
@@ -293,7 +293,6 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
						  unsigned int stage)
{
	u32 cpu_req_feature = cpufeature_probe(stage);
	u32 cpu_apply_feature = 0;
	struct alt_entry *alt;
	u32 tmp;

@@ -307,10 +306,8 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
		}

		tmp = (1U << alt->errata_id);
		if (cpu_req_feature & tmp) {
		if (cpu_req_feature & tmp)
			patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
			cpu_apply_feature |= tmp;
		}
	}
}
#endif