Commit c8236ac9 authored Jan 06, 2025 by Kristina Martsenko Committed by Chen Zhongjin Jan 06, 2025

arm64: probes: Disable kprobes/uprobes on MOPS instructions

stable inclusion
from stable-v6.6.64
commit 0dd9a53bb9b2562c7f73edbca2f399828700b7a6
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IBA6RL

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=0dd9a53bb9b2562c7f73edbca2f399828700b7a6



--------------------------------

[ Upstream commit c56c599d9002d44f559be3852b371db46adac87c ]

FEAT_MOPS instructions require that all three instructions (prologue,
main and epilogue) appear consecutively in memory. Placing a
kprobe/uprobe on one of them doesn't work as only a single instruction
gets executed out-of-line or simulated. So don't allow placing a probe
on a MOPS instruction.

Fixes: b7564127 ("arm64: mops: detect and enable FEAT_MOPS")
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20240930161051.3777828-2-kristina.martsenko@arm.com


Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Chen Zhongjin <chenzhongjin@huawei.com>

parent 82d575a1

arch/arm64/include/asm/insn.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -347,6 +347,7 @@ __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
		__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
		__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
		__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
		__AARCH64_INSN_FUNCS(mops, 0x3B200C00, 0x19000400)
		__AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000)
		__AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)
		__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)

arch/arm64/kernel/probes/decode-insn.c

+5 −2

Original line number	Diff line number	Diff line
		@@ -58,10 +58,13 @@ static bool __kprobes aarch64_insn_is_steppable(u32 insn)
		* Instructions which load PC relative literals are not going to work
		* when executed from an XOL slot. Instructions doing an exclusive
		* load/store are not going to complete successfully when single-step
		* exception handling happens in the middle of the sequence.
		* exception handling happens in the middle of the sequence. Memory
		* copy/set instructions require that all three instructions be placed
		* consecutively in memory.
		*/
		if (aarch64_insn_uses_literal(insn) \|\|
		aarch64_insn_is_exclusive(insn))
		aarch64_insn_is_exclusive(insn) \|\|
		aarch64_insn_is_mops(insn))
		return false;

		return true;