Commit c8227d56 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 

tools/testing/selftests/net/forwarding/Makefile
  f62c5acc ("selftests/net/forwarding: add missing tests to Makefile")
  50fe062c ("selftests: forwarding: new test, verify host mdb entries")
https://lore.kernel.org/all/20220502111539.0b7e4621@canb.auug.org.au/



Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 1c1ed5a4 68533eb1

Documentation/arm64/memory-tagging-extension.rst

+2 −2
Original line number Diff line number Diff line
@@ -228,10 +228,10 @@ Core dump support 
-----------------



The allocation tags for user memory mapped with ``PROT_MTE`` are dumped

in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The

in the core file as additional ``PT_AARCH64_MEMTAG_MTE`` segments. The

program header for such segment is defined as:



:``p_type``: ``PT_ARM_MEMTAG_MTE``

:``p_type``: ``PT_AARCH64_MEMTAG_MTE``

:``p_flags``: 0

:``p_offset``: segment file offset

:``p_vaddr``: segment virtual address, same as the corresponding

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

+11 −2
Original line number Diff line number Diff line
@@ -22,7 +22,16 @@ properties: 
    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1

    items:

      - description: |

          clock config registers:

          These registers contain enable, reset & divider tables for the, cpu,

          axi, ahb and rtc/mtimer reference clocks as well as enable and reset

          for the peripheral clocks.

      - description: |

          mss pll dri registers:

          Block of registers responsible for dynamic reconfiguration of the mss

          pll



  clocks:

    maxItems: 1
@@ -51,7 +60,7 @@ examples: 
            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };

Documentation/devicetree/bindings/hwmon/ti,tmp421.yaml

+3 −4
Original line number Diff line number Diff line
@@ -58,10 +58,9 @@ patternProperties: 
        description: |

          The value (two's complement) to be programmed in the channel specific N correction register.

          For remote channels only.

        $ref: /schemas/types.yaml#/definitions/uint32

        items:

          minimum: 0

          maximum: 255

        $ref: /schemas/types.yaml#/definitions/int32

        minimum: -128

        maximum: 127



    required:

      - reg

Documentation/devicetree/bindings/mfd/atmel-flexcom.txt

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ flexcom@f8034000 { 
		clock-names = "spi_clk";

		atmel,fifo-size = <32>;



		mtd_dataflash@0 {

		flash@0 {

			compatible = "atmel,at25f512b";

			reg = <0>;

			spi-max-frequency = <20000000>;

Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml

+12 −3
Original line number Diff line number Diff line
@@ -31,11 +31,19 @@ properties: 
          to that of the RTC's count register.



  clocks:

    maxItems: 1

    items:

      - description: |

          AHB clock

      - description: |

          Reference clock: divided by the prescaler to create a time-based

          strobe (typically 1 Hz) for the calendar counter. By default, the rtc

          on the PolarFire SoC shares it's reference with MTIMER so this will

          be a 1 MHz clock.



  clock-names:

    items:

      - const: rtc

      - const: rtcref



required:

  - compatible
@@ -48,11 +56,12 @@ additionalProperties: false 


examples:

  - |

    #include "dt-bindings/clock/microchip,mpfs-clock.h"

    rtc@20124000 {

        compatible = "microchip,mpfs-rtc";

        reg = <0x20124000 0x1000>;

        clocks = <&clkcfg 21>;

        clock-names = "rtc";

        clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;

        clock-names = "rtc", "rtcref";

        interrupts = <80>, <81>;

    };

...