Unverified Commit c80ee64a authored by Jisheng Zhang's avatar Jisheng Zhang Committed by Palmer Dabbelt
Browse files

riscv: alternative only works on !XIP_KERNEL 



The alternative mechanism needs runtime code patching, it can't work
on XIP_KERNEL. And the errata workarounds are implemented via the
alternative mechanism. So add !XIP_KERNEL dependency for alternative
and erratas.

Signed-off-by: default avatarJisheng Zhang <jszhang@kernel.org>
Fixes: 44c92257 ("RISC-V: enable XIP")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 74583f1b

arch/riscv/Kconfig.erratas

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ menu "CPU errata selection" 


config RISCV_ERRATA_ALTERNATIVE

	bool "RISC-V alternative scheme"

	depends on !XIP_KERNEL

	default y

	help

	  This Kconfig allows the kernel to automatically patch the

arch/riscv/Kconfig.socs

+2 −2
Original line number Diff line number Diff line
@@ -14,8 +14,8 @@ config SOC_SIFIVE 
	select CLK_SIFIVE

	select CLK_SIFIVE_PRCI

	select SIFIVE_PLIC

	select RISCV_ERRATA_ALTERNATIVE

	select ERRATA_SIFIVE

	select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL

	select ERRATA_SIFIVE if !XIP_KERNEL

	help

	  This enables support for SiFive SoC platform hardware.