Commit c7e34aa3 authored by Daniele Alessandrelli's avatar Daniele Alessandrelli Committed by Herbert Xu
Browse files

dt-bindings: Add Keem Bay OCS AES bindings 



Add device-tree bindings for Intel Keem Bay Offload and Crypto Subsystem
(OCS) AES crypto driver.

Signed-off-by: default avatarDaniele Alessandrelli <daniele.alessandrelli@intel.com>
Acked-by: default avatarMark Gross <mgross@linux.intel.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 0464e0ef

Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml

0 → 100644
+45 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Keem Bay OCS AES Device Tree Bindings



maintainers:

  - Daniele Alessandrelli <daniele.alessandrelli@intel.com>



description:

  The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides

  hardware-accelerated AES/SM4 encryption/decryption.



properties:

  compatible:

    const: intel,keembay-ocs-aes



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts

  - clocks



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    crypto@30008000 {

      compatible = "intel,keembay-ocs-aes";

      reg = <0x30008000 0x1000>;

      interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&scmi_clk 95>;

    };