Commit c7c774fe authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-10-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Cross-subsystem Changes:
- fbdev/efifb: Release PCI device's runtime PM ref during FB destr\
oy (Imre)

i915 Core Driver Changes:
- Only access SFC_DONE in media when not fused off for graphics 12 and newer.
- Double Memory latency values from pcode for DG2 (Matt Roper)
- ADL-S PCI ID update (Tejas)
- New DG1 PCI ID (Jose)
- Fix regression with uncore refactoring (Dave)

i915 Display Changes:
- ADL-P display (XE_LPD) fixes and updates (Ankit, Jani, Matt Roper, Anusham, Jose, Imre, Vandita)
- DG2 display fixes (Ankit, Jani)
- Expand PCH_CNP tweaked display workaround to all newer displays (Anshuman)
- General display simplifications and clean-ups (Jani, Swati, Jose, Ville)
- PSR Clean-ups, dropping support for BDW/HSD and enable PSR2 selective fetch by default (Jose, Gwan-gyeong)
- Nuke ORIGIN_GTT (Jose)
- Return proper DPRX link training result (Lee)
- FBC related refactor and fixes (Ville)
- Yet another attempt to solve the fast+narrow vs slow+wide eDP link training (Kai-Heng)
- DP 2.0 preparation work (Jani)
- Silence __iomem sparse warn (Ville)
- Clean up DPLL stuff (Ville)
- Fix various dp/edp max rates (Matt Atwood, Animesh, Jani)
- Remove VBT ddi_port_info caching (Jani)
- DSI driver improvements (Lee)
- HDCP fixes (Juston)
- Associate ACPI connector nodes with connector entries (Heikki)
- Add support for out-of-bound hotplug events (Hans)
- VESA vendor block and drm/i915 MSO use of it (Jani)
- Fixes for bigjoiner (Ville)
- Update memory bandwidth parameters (RK)
- DMC related fixes (Chris, Jose)
- HDR related fixes and improvements (Tejas)
- g4x/vlv/chv CxSR/wm fixes/cleanups (Ville)
- Use BIOS provided value for RKL Audio's HDA link (Kai-Heng)
- Fix the dsc check while selecting min_cdclk (Vandita)
- Split and constify vtable (Dave)
- Add ww context to intel_dpt_pin (Maarten)
- Fix bdb version check (Lukasz)
- DP per-lane drive settings prep work and other DP fixes (Ville)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

# gpg: Signature made Tue 05 Oct 2021 04:58:16 AEST
# gpg:                using RSA key 6D207068EEDD65091C2CE2A3FA625F640EEB13CA
# gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" [unknown]
# gpg:                 aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C  E2A3 FA62 5F64 0EEB 13CA
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YVtPk6llsxBFiw7W@intel.com
parents 797d72ce 104c1b3d

Documentation/gpu/i915.rst

+11 −14
Original line number Diff line number Diff line
@@ -183,26 +183,23 @@ Frame Buffer Compression (FBC) 
Display Refresh Rate Switching (DRRS)

-------------------------------------



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :doc: Display Refresh Rate Switching (DRRS)



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_dp_set_drrs_state

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_enable



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_edp_drrs_enable

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_disable



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_edp_drrs_disable

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_invalidate



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_edp_drrs_invalidate

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_flush



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_edp_drrs_flush



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp.c

   :functions: intel_dp_drrs_init

.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_init



DPIO

----

drivers/gpu/drm/drm_dp_helper.c

+37 −5
Original line number Diff line number Diff line
@@ -130,6 +130,20 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI 
}

EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);



/* DP 2.0 128b/132b */

u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],

				   int lane)

{

	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

	int s = ((lane & 1) ?

		 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :

		 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);

	u8 l = dp_link_status(link_status, i);



	return (l >> s) & 0xf;

}

EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);



u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],

					 unsigned int lane)

{
@@ -207,16 +221,34 @@ EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 


u8 drm_dp_link_rate_to_bw_code(int link_rate)

{

	switch (link_rate) {

	case 1000000:

		return DP_LINK_BW_10;

	case 1350000:

		return DP_LINK_BW_13_5;

	case 2000000:

		return DP_LINK_BW_20;

	default:

		/* Spec says link_bw = link_rate / 0.27Gbps */

		return link_rate / 27000;

	}

}

EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);



int drm_dp_bw_code_to_link_rate(u8 link_bw)

{

	switch (link_bw) {

	case DP_LINK_BW_10:

		return 1000000;

	case DP_LINK_BW_13_5:

		return 1350000;

	case DP_LINK_BW_20:

		return 2000000;

	default:

		/* Spec says link_rate = link_bw * 0.27Gbps */

		return link_bw * 27000;

	}

}

EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);



#define AUX_RETRY_INTERVAL 500 /* us */
@@ -590,7 +622,7 @@ static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 
static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,

					  u8 dpcd[DP_RECEIVER_CAP_SIZE])

{

	u8 dpcd_ext[6];

	u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];

	int ret;



	/*

drivers/gpu/drm/drm_edid.c

+79 −10
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
 * DEALINGS IN THE SOFTWARE.

 */



#include <linux/bitfield.h>

#include <linux/hdmi.h>

#include <linux/i2c.h>

#include <linux/kernel.h>
@@ -49,6 +50,11 @@ 
	(((edid)->version > (maj)) || \

	 ((edid)->version == (maj) && (edid)->revision > (min)))



static int oui(u8 first, u8 second, u8 third)

{

	return (first << 16) | (second << 8) | third;

}



#define EDID_EST_TIMINGS 16

#define EDID_STD_TIMINGS 8

#define EDID_DETAILED_TIMINGS 4
@@ -4187,32 +4193,24 @@ cea_db_offsets(const u8 *cea, int *start, int *end) 


static bool cea_db_is_hdmi_vsdb(const u8 *db)

{

	int hdmi_id;



	if (cea_db_tag(db) != VENDOR_BLOCK)

		return false;



	if (cea_db_payload_len(db) < 5)

		return false;



	hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);



	return hdmi_id == HDMI_IEEE_OUI;

	return oui(db[3], db[2], db[1]) == HDMI_IEEE_OUI;

}



static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)

{

	unsigned int oui;



	if (cea_db_tag(db) != VENDOR_BLOCK)

		return false;



	if (cea_db_payload_len(db) < 7)

		return false;



	oui = db[3] << 16 | db[2] << 8 | db[1];



	return oui == HDMI_FORUM_IEEE_OUI;

	return oui(db[3], db[2], db[1]) == HDMI_FORUM_IEEE_OUI;

}



static bool cea_db_is_vcdb(const u8 *db)
@@ -5222,6 +5220,71 @@ void drm_get_monitor_range(struct drm_connector *connector, 
		      info->monitor_range.max_vfreq);

}



static void drm_parse_vesa_mso_data(struct drm_connector *connector,

				    const struct displayid_block *block)

{

	struct displayid_vesa_vendor_specific_block *vesa =

		(struct displayid_vesa_vendor_specific_block *)block;

	struct drm_display_info *info = &connector->display_info;



	if (block->num_bytes < 3) {

		drm_dbg_kms(connector->dev, "Unexpected vendor block size %u\n",

			    block->num_bytes);

		return;

	}



	if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)

		return;



	if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {

		drm_dbg_kms(connector->dev, "Unexpected VESA vendor block size\n");

		return;

	}



	switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {

	default:

		drm_dbg_kms(connector->dev, "Reserved MSO mode value\n");

		fallthrough;

	case 0:

		info->mso_stream_count = 0;

		break;

	case 1:

		info->mso_stream_count = 2; /* 2 or 4 links */

		break;

	case 2:

		info->mso_stream_count = 4; /* 4 links */

		break;

	}



	if (!info->mso_stream_count) {

		info->mso_pixel_overlap = 0;

		return;

	}



	info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);

	if (info->mso_pixel_overlap > 8) {

		drm_dbg_kms(connector->dev, "Reserved MSO pixel overlap value %u\n",

			    info->mso_pixel_overlap);

		info->mso_pixel_overlap = 8;

	}



	drm_dbg_kms(connector->dev, "MSO stream count %u, pixel overlap %u\n",

		    info->mso_stream_count, info->mso_pixel_overlap);

}



static void drm_update_mso(struct drm_connector *connector, const struct edid *edid)

{

	const struct displayid_block *block;

	struct displayid_iter iter;



	displayid_iter_edid_begin(edid, &iter);

	displayid_iter_for_each(block, &iter) {

		if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)

			drm_parse_vesa_mso_data(connector, block);

	}

	displayid_iter_end(&iter);

}



/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset

 * all of the values which would have been set from EDID

 */
@@ -5245,6 +5308,9 @@ drm_reset_display_info(struct drm_connector *connector) 


	info->non_desktop = 0;

	memset(&info->monitor_range, 0, sizeof(info->monitor_range));



	info->mso_stream_count = 0;

	info->mso_pixel_overlap = 0;

}



u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
@@ -5323,6 +5389,9 @@ u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edi 
		info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;

	if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)

		info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;



	drm_update_mso(connector, edid);



	return quirks;

}

drivers/gpu/drm/i915/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -211,6 +211,8 @@ i915-y += \ 
	display/intel_dpio_phy.o \

	display/intel_dpll.o \

	display/intel_dpll_mgr.o \

	display/intel_dpt.o \

	display/intel_drrs.o \

	display/intel_dsb.o \

	display/intel_fb.o \

	display/intel_fbc.o \
@@ -247,6 +249,7 @@ i915-y += \ 
	display/g4x_dp.o \

	display/g4x_hdmi.o \

	display/icl_dsi.o \

	display/intel_backlight.o \

	display/intel_crt.o \

	display/intel_ddi.o \

	display/intel_ddi_buf_trans.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+42 −44
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include "g4x_dp.h"

#include "intel_audio.h"

#include "intel_backlight.h"

#include "intel_connector.h"

#include "intel_de.h"

#include "intel_display_types.h"
@@ -16,7 +17,6 @@ 
#include "intel_fifo_underrun.h"

#include "intel_hdmi.h"

#include "intel_hotplug.h"

#include "intel_panel.h"

#include "intel_pps.h"

#include "intel_sideband.h"
@@ -211,7 +211,7 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, 
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



	assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);

	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);

	assert_dp_port_disabled(intel_dp);

	assert_edp_pll_disabled(dev_priv);
@@ -251,7 +251,7 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, 
	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);



	assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);

	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);

	assert_dp_port_disabled(intel_dp);

	assert_edp_pll_enabled(dev_priv);
@@ -426,7 +426,6 @@ intel_dp_link_down(struct intel_encoder *encoder, 
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);

	enum port port = encoder->port;

	u32 DP = intel_dp->DP;



	if (drm_WARN_ON(&dev_priv->drm,

			(intel_de_read(dev_priv, intel_dp->output_reg) &
@@ -437,17 +436,17 @@ intel_dp_link_down(struct intel_encoder *encoder, 


	if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||

	    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {

		DP &= ~DP_LINK_TRAIN_MASK_CPT;

		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

		intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

	} else {

		DP &= ~DP_LINK_TRAIN_MASK;

		DP |= DP_LINK_TRAIN_PAT_IDLE;

		intel_dp->DP &= ~DP_LINK_TRAIN_MASK;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;

	}

	intel_de_write(dev_priv, intel_dp->output_reg, DP);

	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);



	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);

	intel_de_write(dev_priv, intel_dp->output_reg, DP);

	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);

	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

	intel_de_posting_read(dev_priv, intel_dp->output_reg);



	/*
@@ -464,14 +463,14 @@ intel_dp_link_down(struct intel_encoder *encoder, 
		intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);



		/* always enable with pattern 1 (as per spec) */

		DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

		DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

		intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

		intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

			DP_LINK_TRAIN_PAT_1;

		intel_de_write(dev_priv, intel_dp->output_reg, DP);

		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(dev_priv, intel_dp->output_reg);



		DP &= ~DP_PORT_EN;

		intel_de_write(dev_priv, intel_dp->output_reg, DP);

		intel_dp->DP &= ~DP_PORT_EN;

		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);

		intel_de_posting_read(dev_priv, intel_dp->output_reg);



		intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
@@ -481,8 +480,6 @@ intel_dp_link_down(struct intel_encoder *encoder, 


	msleep(intel_dp->pps.panel_power_down_delay);



	intel_dp->DP = DP;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {

		intel_wakeref_t wakeref;
@@ -582,19 +579,18 @@ cpt_set_link_train(struct intel_dp *intel_dp, 
		   u8 dp_train_pat)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u32 *DP = &intel_dp->DP;



	*DP &= ~DP_LINK_TRAIN_MASK_CPT;

	intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;



	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {

	case DP_TRAINING_PATTERN_DISABLE:

		*DP |= DP_LINK_TRAIN_OFF_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		break;

	case DP_TRAINING_PATTERN_1:

		*DP |= DP_LINK_TRAIN_PAT_1_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;

		break;

	case DP_TRAINING_PATTERN_2:

		*DP |= DP_LINK_TRAIN_PAT_2_CPT;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;

		break;

	default:

		MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
@@ -611,19 +607,18 @@ g4x_set_link_train(struct intel_dp *intel_dp, 
		   u8 dp_train_pat)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	u32 *DP = &intel_dp->DP;



	*DP &= ~DP_LINK_TRAIN_MASK;

	intel_dp->DP &= ~DP_LINK_TRAIN_MASK;



	switch (intel_dp_training_pattern_symbol(dp_train_pat)) {

	case DP_TRAINING_PATTERN_DISABLE:

		*DP |= DP_LINK_TRAIN_OFF;

		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		break;

	case DP_TRAINING_PATTERN_1:

		*DP |= DP_LINK_TRAIN_PAT_1;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_1;

		break;

	case DP_TRAINING_PATTERN_2:

		*DP |= DP_LINK_TRAIN_PAT_2;

		intel_dp->DP |= DP_LINK_TRAIN_PAT_2;

		break;

	default:

		MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
@@ -813,10 +808,10 @@ static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp) 
	return DP_TRAIN_PRE_EMPH_LEVEL_3;

}



static void vlv_set_signal_levels(struct intel_dp *intel_dp,

static void vlv_set_signal_levels(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state)

{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	unsigned long demph_reg_value, preemph_reg_value,

		uniqtranscale_reg_value;

	u8 train_set = intel_dp->train_set[0];
@@ -899,10 +894,10 @@ static void vlv_set_signal_levels(struct intel_dp *intel_dp, 
				 uniqtranscale_reg_value, 0);

}



static void chv_set_signal_levels(struct intel_dp *intel_dp,

static void chv_set_signal_levels(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state)

{

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 deemph_reg_value, margin_reg_value;

	bool uniq_trans_scale = false;

	u8 train_set = intel_dp->train_set[0];
@@ -1020,10 +1015,11 @@ static u32 g4x_signal_levels(u8 train_set) 
}



static void

g4x_set_signal_levels(struct intel_dp *intel_dp,

g4x_set_signal_levels(struct intel_encoder *encoder,

		      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;
@@ -1067,10 +1063,11 @@ static u32 snb_cpu_edp_signal_levels(u8 train_set) 
}



static void

snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,

snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;
@@ -1118,10 +1115,11 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set) 
}



static void

ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,

ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u8 train_set = intel_dp->train_set[0];

	u32 signal_levels;
@@ -1334,7 +1332,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
	intel_encoder->get_config = intel_dp_get_config;

	intel_encoder->sync_state = intel_dp_sync_state;

	intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;

	intel_encoder->update_pipe = intel_panel_update_backlight;

	intel_encoder->update_pipe = intel_backlight_update;

	intel_encoder->suspend = intel_dp_encoder_suspend;

	intel_encoder->shutdown = intel_dp_encoder_shutdown;

	if (IS_CHERRYVIEW(dev_priv)) {
@@ -1364,15 +1362,15 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, 
		dig_port->dp.set_link_train = g4x_set_link_train;



	if (IS_CHERRYVIEW(dev_priv))

		dig_port->dp.set_signal_levels = chv_set_signal_levels;

		intel_encoder->set_signal_levels = chv_set_signal_levels;

	else if (IS_VALLEYVIEW(dev_priv))

		dig_port->dp.set_signal_levels = vlv_set_signal_levels;

		intel_encoder->set_signal_levels = vlv_set_signal_levels;

	else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)

		dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;

		intel_encoder->set_signal_levels = ivb_cpu_edp_set_signal_levels;

	else if (IS_SANDYBRIDGE(dev_priv) && port == PORT_A)

		dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;

		intel_encoder->set_signal_levels = snb_cpu_edp_set_signal_levels;

	else

		dig_port->dp.set_signal_levels = g4x_set_signal_levels;

		intel_encoder->set_signal_levels = g4x_set_signal_levels;



	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||

	    (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {