Commit c7b75bea authored by Jiawen Wu's avatar Jiawen Wu Committed by David S. Miller
Browse files

net: phy: marvell10g: fix 88x3310 power up 



Clear MV_V2_PORT_CTRL_PWRDOWN bit to set power up for 88x3310 PHY,
it sometimes does not take effect immediately. And a read of this
register causes the bit not to clear. This will cause mv3310_reset()
to time out, which will fail the config initialization. So add a delay
before the next access.

Fixes: c9cc1c81 ("net: phy: marvell10g: place in powersave mode at probe")
Signed-off-by: default avatarJiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 32ad45b7

drivers/net/phy/marvell10g.c

+7 −0
Original line number Diff line number Diff line
@@ -328,6 +328,13 @@ static int mv3310_power_up(struct phy_device *phydev) 
	ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,

				 MV_V2_PORT_CTRL_PWRDOWN);



	/* Sometimes, the power down bit doesn't clear immediately, and

	 * a read of this register causes the bit not to clear. Delay

	 * 100us to allow the PHY to come out of power down mode before

	 * the next access.

	 */

	udelay(100);



	if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||

	    priv->firmware_ver < 0x00030000)

		return ret;