Commit c7a9dcea authored by Palmer Dabbelt's avatar Palmer Dabbelt Committed by Will Deacon
Browse files

perf: RISC-V: Remove non-kernel-doc ** comments 



This will presumably trip up some tools that try to parse the comments
as kernel doc when they're not.

Reported-by: default avatarkernel test robot <lkp@intel.com>
Fixes: 4905ec2f ("RISC-V: Add sscofpmf extension support")
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>

--

These recently landed in for-next, but I'm trying to avoid rewriting
history as there's a lot in flight right now.

Reviewed-by: default avatarAtish Patra <atishp@rivosinc.com>
Acked-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20220322220147.11407-1-palmer@rivosinc.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b2d229d4

drivers/perf/riscv_pmu_sbi.c

+4 −4
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ union sbi_pmu_ctr_info { 
	};

};



/**

/*

 * RISC-V doesn't have hetergenous harts yet. This need to be part of

 * per_cpu in case of harts with different pmu counters

 */
@@ -477,7 +477,7 @@ static int pmu_sbi_get_ctrinfo(int nctr) 


static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)

{

	/**

	/*

	 * No need to check the error because we are disabling all the counters

	 * which may include counters that are not enabled yet.

	 */
@@ -494,7 +494,7 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) 
		  cpu_hw_evt->used_hw_ctrs[0], 0, 0, 0, 0);

}



/**

/*

 * This function starts all the used counters in two step approach.

 * Any counter that did not overflow can be start in a single step

 * while the overflowed counters need to be started with updated initialization
@@ -563,7 +563,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) 
	/* Overflow status register should only be read after counter are stopped */

	overflow = csr_read(CSR_SSCOUNTOVF);



	/**

	/*

	 * Overflow interrupt pending bit should only be cleared after stopping

	 * all the counters to avoid any race condition.

	 */