Merge branch 'pci/trivial'

// SPDX-License-Identifier: GPL-2.0

/*

 * Simple, generic PCI host controller driver targetting firmware-initialised

 * Simple, generic PCI host controller driver targeting firmware-initialised

 * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).

 *

 * Copyright (C) 2014 ARM Limited

		/*

		 * Now go read the tail pointer again to see if there are new

		 * oustanding events that came in during the above window.

		 * outstanding events that came in during the above window.

		 */

	} while (true);

 * Tell if a device supports a given PCI capability.

 * Returns the address of the requested capability structure within the

 * device's PCI configuration space or 0 in case the device does not

 * support it.  Possible values for @cap:

 * support it.  Possible values for @cap include:

 *

 *  %PCI_CAP_ID_PM           Power Management

 *  %PCI_CAP_ID_AGP          Accelerated Graphics Port

 * @devfn: PCI device to query

 * @cap: capability code

 *

 * Like pci_find_capability() but works for pci devices that do not have a

 * Like pci_find_capability() but works for PCI devices that do not have a

 * pci_dev structure set up yet.

 *

 * Returns the address of the requested capability structure within the

 *

 * Returns the address of the requested extended capability structure

 * within the device's PCI configuration space or 0 if the device does

 * not support it.  Possible values for @cap:

 * not support it.  Possible values for @cap include:

 *

 *  %PCI_EXT_CAP_ID_ERR		Advanced Error Reporting

 *  %PCI_EXT_CAP_ID_VC		Virtual Channel

EXPORT_SYMBOL_GPL(pci_find_ht_capability);

/**

 * pci_find_parent_resource - return resource region of parent bus of given region

 * pci_find_parent_resource - return resource region of parent bus of given

 *			      region

 * @dev: PCI device structure contains resources to be searched

 * @res: child resource record for which parent is sought

 *

 *  For given resource region of given device, return the resource

 *  region of parent bus the given region is contained in.

 * For given resource region of given device, return the resource region of

 * parent bus the given region is contained in.

 */

struct resource *pci_find_parent_resource(const struct pci_dev *dev,

					  struct resource *res)

	if (state < PCI_D0 || state > PCI_D3hot)

		return -EINVAL;

	/* Validate current state:

	/*

	 * Validate current state:

	 * Can enter D0 from any state, but if we can only go deeper

	 * to sleep if we're already in a low power state

	 */

		return -EINVAL;

	}

	/* check if this device supports the desired state */

	/* Check if this device supports the desired state */

	if ((state == PCI_D1 && !dev->d1_support)

	   || (state == PCI_D2 && !dev->d2_support))

		return -EIO;

	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);

	/* If we're (effectively) in D3, force entire word to 0.

	/*

	 * If we're (effectively) in D3, force entire word to 0.

	 * This doesn't affect PME_Status, disables PME_En, and

	 * sets PowerState to 0.

	 */

		break;

	}

	/* enter specified state */

	/* Enter specified state */

	pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);

	/* Mandatory power management transition delays */

	/* see PCI PM 1.1 5.6.1 table 18 */

	/*

	 * Mandatory power management transition delays; see PCI PM 1.1

	 * 5.6.1 table 18

	 */

	if (state == PCI_D3hot || dev->current_state == PCI_D3hot)

		pci_dev_d3_sleep(dev);

	else if (state == PCI_D2 || dev->current_state == PCI_D2)

{

	int error;

	/* bound the state we're entering */

	/* Bound the state we're entering */

	if (state > PCI_D3cold)

		state = PCI_D3cold;

	else if (state < PCI_D0)

		state = PCI_D0;

	else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))

		/*

		 * If the device or the parent bridge do not support PCI PM,

		 * ignore the request if we're doing anything other than putting

		 * it into D0 (which would only happen on boot).

		 * If the device or the parent bridge do not support PCI

		 * PM, ignore the request if we're doing anything other

		 * than putting it into D0 (which would only happen on

		 * boot).

		 */

		return 0;

	__pci_start_power_transition(dev, state);

	/* This device is quirked not to be put into D3, so

	   don't put it in D3 */

	/*

	 * This device is quirked not to be put into D3, so don't put it in

	 * D3

	 */

	if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))

		return 0;

 * Returns PCI power state suitable for given device and given system

 * message.

 */

pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)

{

	pci_power_t ret;

}

/**

 * pci_save_state - save the PCI configuration space of a device before suspending

 * @dev: - PCI device that we're dealing with

 * pci_save_state - save the PCI configuration space of a device before

 *		    suspending

 * @dev: PCI device that we're dealing with

 */

int pci_save_state(struct pci_dev *dev)

{

/**

 * pci_restore_state - Restore the saved state of a PCI device

 * @dev: - PCI device that we're dealing with

 * @dev: PCI device that we're dealing with

 */

void pci_restore_state(struct pci_dev *dev)

{

 * pci_reenable_device - Resume abandoned device

 * @dev: PCI device to be resumed

 *

 *  Note this function is a backend of pci_default_resume and is not supposed

 * NOTE: This function is a backend of pci_default_resume() and is not supposed

 * to be called by normal code, write proper resume handler and use it instead.

 */

int pci_reenable_device(struct pci_dev *dev)

EXPORT_SYMBOL(pci_enable_device);

/*

 * Managed PCI resources.  This manages device on/off, intx/msi/msix

 * on/off and BAR regions.  pci_dev itself records msi/msix status, so

 * Managed PCI resources.  This manages device on/off, INTx/MSI/MSI-X

 * on/off and BAR regions.  pci_dev itself records MSI/MSI-X status, so

 * there's no need to track it separately.  pci_devres is initialized

 * when a device is enabled using managed PCI device enable interface.

 */

}

/**

 * pcibios_release_device - provide arch specific hooks when releasing device dev

 * pcibios_release_device - provide arch specific hooks when releasing

 *			    device dev

 * @dev: the PCI device being released

 *

 * Permits the platform to provide architecture specific functionality when

 * @dev: the PCIe device reset

 * @state: Reset state to enter into

 *

 *

 * Sets the PCIe reset state for the device. This is the default

 * Set the PCIe reset state for the device. This is the default

 * implementation. Architecture implementations can override this.

 */

int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,

 * @dev: the PCIe device reset

 * @state: Reset state to enter into

 *

 *

 * Sets the PCI reset state for the device.

 */

int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)

}

/**

 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state

 * pci_prepare_to_sleep - prepare PCI device for system-wide transition

 *			  into a sleep state

 * @dev: Device to handle.

 *

 * Choose the power state appropriate for the device depending on whether

EXPORT_SYMBOL(pci_prepare_to_sleep);

/**

 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state

 * pci_back_from_sleep - turn PCI device on during system-wide transition

 *			 into working state

 * @dev: Device to handle.

 *

 * Disable device's system wake-up capability and put it into D0.

}

/**

 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites

 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities

 * @dev: the PCI device

 */

static void pci_std_enable_acs(struct pci_dev *dev)

/**

 * pci_release_region - Release a PCI bar

 *	@pdev: PCI device whose resources were previously reserved by pci_request_region

 * @pdev: PCI device whose resources were previously reserved by

 *	  pci_request_region()

 * @bar: BAR to release

 *

 * Releases the PCI I/O and memory resources previously reserved by a

 *	successful call to pci_request_region.  Call this function only

 * successful call to pci_request_region().  Call this function only

 * after all use of the PCI regions has ceased.

 */

void pci_release_region(struct pci_dev *pdev, int bar)

 * @res_name: Name to be associated with resource.

 * @exclusive: whether the region access is exclusive or not

 *

 *	Mark the PCI region associated with PCI device @pdev BR @bar as

 * Mark the PCI region associated with PCI device @pdev BAR @bar as

 * being reserved by owner @res_name.  Do not access any

 * address inside the PCI regions unless this call returns

 * successfully.

/**

 * pci_release_regions - Release reserved PCI I/O and memory resources

 *	@pdev: PCI device whose resources were previously reserved by pci_request_regions

 * @pdev: PCI device whose resources were previously reserved by

 *	  pci_request_regions()

 *

 * Releases all PCI I/O and memory resources previously reserved by a

 *	successful call to pci_request_regions.  Call this function only

 * successful call to pci_request_regions().  Call this function only

 * after all use of the PCI regions has ceased.

 */

EXPORT_SYMBOL(pci_release_regions);

/**

 *	pci_request_regions - Reserved PCI I/O and memory resources

 * pci_request_regions - Reserve PCI I/O and memory resources

 * @pdev: PCI device whose resources are to be reserved

 * @res_name: Name to be associated with resource.

 *

EXPORT_SYMBOL(pci_request_regions);

/**

 *	pci_request_regions_exclusive - Reserved PCI I/O and memory resources

 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources

 * @pdev: PCI device whose resources are to be reserved

 * @res_name: Name to be associated with resource.

 *

 *	Mark all PCI regions associated with PCI device @pdev as

 *	being reserved by owner @res_name.  Do not access any

 *	address inside the PCI regions unless this call returns

 *	successfully.

 * Mark all PCI regions associated with PCI device @pdev as being reserved

 * by owner @res_name.  Do not access any address inside the PCI regions

 * unless this call returns successfully.

 *

 *	pci_request_regions_exclusive() will mark the region so that

 *	/dev/mem and the sysfs MMIO access will not be allowed.

 * pci_request_regions_exclusive() will mark the region so that /dev/mem

 * and the sysfs MMIO access will not be allowed.

 *

 *	Returns 0 on success, or %EBUSY on error.  A warning

 *	message is also printed on failure.

 * Returns 0 on success, or %EBUSY on error.  A warning message is also

 * printed on failure.

 */

int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)

{

/*

 * Record the PCI IO range (expressed as CPU physical address + size).

 * Return a negative value if an error has occured, zero otherwise

 * Return a negative value if an error has occurred, zero otherwise

 */

int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,

			resource_size_t	size)

 * @res: Resource describing the I/O space

 * @phys_addr: physical address of range to be mapped

 *

 *	Remap the memory mapped I/O space described by the @res

 *	and the CPU physical address @phys_addr into virtual address space.

 *	Only architectures that have memory mapped IO functions defined

 *	(and the PCI_IOBASE value defined) should call this function.

 * Remap the memory mapped I/O space described by the @res and the CPU

 * physical address @phys_addr into virtual address space.  Only

 * architectures that have memory mapped IO functions defined (and the

 * PCI_IOBASE value defined) should call this function.

 */

int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)

{

	return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,

				  pgprot_device(PAGE_KERNEL));

#else

	/* this architecture does not have memory mapped I/O space,

	   so this function should never be called */

	/*

	 * This architecture does not have memory mapped I/O space,

	 * so this function should never be called

	 */

	WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");

	return -ENODEV;

#endif

 * pci_unmap_iospace - Unmap the memory mapped I/O space

 * @res: resource to be unmapped

 *

 *	Unmap the CPU virtual address @res from virtual address space.

 *	Only architectures that have memory mapped IO functions defined

 *	(and the PCI_IOBASE value defined) should call this function.

 * Unmap the CPU virtual address @res from virtual address space.  Only

 * architectures that have memory mapped IO functions defined (and the

 * PCI_IOBASE value defined) should call this function.

 */

void pci_unmap_iospace(struct resource *res)

{

 * @pdev: the PCI device to operate on

 * @enable: boolean: whether to enable or disable PCI INTx

 *

 * Enables/disables PCI INTx for device dev

 * Enables/disables PCI INTx for device @pdev

 */

void pci_intx(struct pci_dev *pdev, int enable)

{

 * pci_check_and_mask_intx - mask INTx on pending interrupt

 * @dev: the PCI device to operate on

 *

 * Check if the device dev has its INTx line asserted, mask it and

 * return true in that case. False is returned if no interrupt was

 * pending.

 * Check if the device dev has its INTx line asserted, mask it and return

 * true in that case. False is returned if no interrupt was pending.

 */

bool pci_check_and_mask_intx(struct pci_dev *dev)

{

 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending

 * @dev: the PCI device to operate on

 *

 * Check if the device dev has its INTx line asserted, unmask it if not

 * and return true. False is returned and the mask remains active if

 * there was still an interrupt pending.

 * Check if the device dev has its INTx line asserted, unmask it if not and

 * return true. False is returned and the mask remains active if there was

 * still an interrupt pending.

 */

bool pci_check_and_unmask_intx(struct pci_dev *dev)

{

EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);

/**

 * pci_wait_for_pending_transaction - waits for pending transaction

 * pci_wait_for_pending_transaction - wait for pending transaction

 * @dev: the PCI device to operate on

 *

 * Return 0 if transaction is pending 1 otherwise.

 *

 * The device function is presumed to be unused and the caller is holding

 * the device mutex lock when this function is called.

 *

 * Resetting the device will make the contents of PCI configuration space

 * random, so any caller of this must be prepared to reinitialise the

 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,

 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count

 * @dev: PCI device to query

 *

 * Returns mmrbc: maximum designed memory read count in bytes

 *    or appropriate error value.

 * Returns mmrbc: maximum designed memory read count in bytes or

 * appropriate error value.

 */

int pcix_get_max_mmrbc(struct pci_dev *dev)

{

 * pcix_get_mmrbc - get PCI-X maximum memory read byte count

 * @dev: PCI device to query

 *

 * Returns mmrbc: maximum memory read count in bytes

 *    or appropriate error value.

 * Returns mmrbc: maximum memory read count in bytes or appropriate error

 * value.

 */

int pcix_get_mmrbc(struct pci_dev *dev)

{

 * @mmrbc: maximum memory read count in bytes

 *    valid values are 512, 1024, 2048, 4096

 *

 * If possible sets maximum memory read byte count, some bridges have erratas

 * If possible sets maximum memory read byte count, some bridges have errata

 * that prevent this.

 */

int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)

 * pcie_get_readrq - get PCI Express read request size

 * @dev: PCI device to query

 *

 * Returns maximum memory read request in bytes

 *    or appropriate error value.

 * Returns maximum memory read request in bytes or appropriate error value.

 */

int pcie_get_readrq(struct pci_dev *dev)

{

		return -EINVAL;

	/*

	 * If using the "performance" PCIe config, we clamp the

	 * read rq size to the max packet size to prevent the

	 * host bridge generating requests larger than we can

	 * cope with

	 * If using the "performance" PCIe config, we clamp the read rq

	 * size to the max packet size to keep the host bridge from

	 * generating requests larger than we can cope with.

	 */

	if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {

		int mps = pcie_get_mps(dev);

	if (parent)

		domain = of_get_pci_domain_nr(parent->of_node);

	/*

	 * Check DT domain and use_dt_domains values.

	 *

 */

#define CPER_REC_LEN					256

/*

 * Severity difinition for error_severity in struct cper_record_header

 * Severity definition for error_severity in struct cper_record_header

 * and section_severity in struct cper_section_descriptor

 */

enum {

};

/*

 * Validation bits difinition for validation_bits in struct

 * Validation bits definition for validation_bits in struct

 * cper_record_header. If set, corresponding fields in struct

 * cper_record_header contain valid information.

 *

 * corresponds platform_id

 */

#define CPER_VALID_PLATFORM_ID			0x0001

/* corresponds timestamp */

#define CPER_VALID_TIMESTAMP			0x0002

/* corresponds partition_id */

#define CPER_VALID_PARTITION_ID			0x0004

/*

 * Notification type used to generate error record, used in

 * notification_type in struct cper_record_header

 *

 * Corrected Machine Check

 * notification_type in struct cper_record_header.  These UUIDs are defined

 * in the UEFI spec v2.7, sec N.2.1.

 */

/* Corrected Machine Check */

#define CPER_NOTIFY_CMC							\

	GUID_INIT(0x2DCE8BB1, 0xBDD7, 0x450e, 0xB9, 0xAD, 0x9C, 0xF4,	\

		  0xEB, 0xD4, 0xF8, 0x90)

#define CPER_SEC_REV				0x0100

/*

 * Validation bits difinition for validation_bits in struct

 * Validation bits definition for validation_bits in struct

 * cper_section_descriptor. If set, corresponding fields in struct

 * cper_section_descriptor contain valid information.

 *

 * corresponds fru_id

 */

#define CPER_SEC_VALID_FRU_ID			0x1

/* corresponds fru_text */

#define CPER_SEC_VALID_FRU_TEXT			0x2

/*

/*

 * Section type definitions, used in section_type field in struct

 * cper_section_descriptor

 *

 * Processor Generic

 * cper_section_descriptor.  These UUIDs are defined in the UEFI spec

 * v2.7, sec N.2.2.

 */

/* Processor Generic */

#define CPER_SEC_PROC_GENERIC						\

	GUID_INIT(0x9876CCAD, 0x47B4, 0x4bdb, 0xB6, 0x5E, 0x16, 0xF1,	\

		  0x93, 0xC4, 0xF3, 0xDB)

 */

#pragma pack(1)

/* Record Header, UEFI v2.7 sec N.2.1 */

struct cper_record_header {

	char	signature[CPER_SIG_SIZE];	/* must be CPER_SIG_RECORD */

	__u16	revision;			/* must be CPER_RECORD_REV */

	__u32	signature_end;			/* must be CPER_SIG_END */

	__u16	section_count;

	__u32	error_severity;

	__u32	validation_bits;

	__u32	record_length;

	__u64	timestamp;

	u16	revision;			/* must be CPER_RECORD_REV */

	u32	signature_end;			/* must be CPER_SIG_END */

	u16	section_count;

	u32	error_severity;

	u32	validation_bits;

	u32	record_length;

	u64	timestamp;

	guid_t	platform_id;

	guid_t	partition_id;

	guid_t	creator_id;

	guid_t	notification_type;

	__u64	record_id;

	__u32	flags;

	__u64	persistence_information;

	__u8	reserved[12];			/* must be zero */

	u64	record_id;

	u32	flags;

	u64	persistence_information;

	u8	reserved[12];			/* must be zero */

};

/* Section Descriptor, UEFI v2.7 sec N.2.2 */

struct cper_section_descriptor {

	__u32	section_offset;		/* Offset in bytes of the

	u32	section_offset;		/* Offset in bytes of the

					 *  section body from the base

					 *  of the record header */

	__u32	section_length;

	__u16	revision;		/* must be CPER_RECORD_REV */

	__u8	validation_bits;

	__u8	reserved;		/* must be zero */

	__u32	flags;

	u32	section_length;

	u16	revision;		/* must be CPER_RECORD_REV */

	u8	validation_bits;

	u8	reserved;		/* must be zero */

	u32	flags;

	guid_t	section_type;

	guid_t	fru_id;

	__u32	section_severity;

	__u8	fru_text[20];

	u32	section_severity;

	u8	fru_text[20];

};

/* Generic Processor Error Section */

/* Generic Processor Error Section, UEFI v2.7 sec N.2.4.1 */

struct cper_sec_proc_generic {

	__u64	validation_bits;

	__u8	proc_type;

	__u8	proc_isa;

	__u8	proc_error_type;

	__u8	operation;

	__u8	flags;

	__u8	level;

	__u16	reserved;

	__u64	cpu_version;

	u64	validation_bits;

	u8	proc_type;

	u8	proc_isa;

	u8	proc_error_type;

	u8	operation;

	u8	flags;

	u8	level;

	u16	reserved;

	u64	cpu_version;

	char	cpu_brand[128];

	__u64	proc_id;

	__u64	target_addr;

	__u64	requestor_id;

	__u64	responder_id;

	__u64	ip;

	u64	proc_id;

	u64	target_addr;

	u64	requestor_id;

	u64	responder_id;

	u64	ip;

};

/* IA32/X64 Processor Error Section */

/* IA32/X64 Processor Error Section, UEFI v2.7 sec N.2.4.2 */

struct cper_sec_proc_ia {

	__u64	validation_bits;

	__u64	lapic_id;

	__u8	cpuid[48];

	u64	validation_bits;

	u64	lapic_id;

	u8	cpuid[48];

};

/* IA32/X64 Processor Error Information Structure */

/* IA32/X64 Processor Error Information Structure, UEFI v2.7 sec N.2.4.2.1 */

struct cper_ia_err_info {

	guid_t	err_type;

	__u64	validation_bits;

	__u64	check_info;

	__u64	target_id;

	__u64	requestor_id;

	__u64	responder_id;

	__u64	ip;

	u64	validation_bits;

	u64	check_info;

	u64	target_id;

	u64	requestor_id;

	u64	responder_id;

	u64	ip;

};

/* IA32/X64 Processor Context Information Structure */

/* IA32/X64 Processor Context Information Structure, UEFI v2.7 sec N.2.4.2.2 */

struct cper_ia_proc_ctx {

	__u16	reg_ctx_type;

	__u16	reg_arr_size;

	__u32	msr_addr;

	__u64	mm_reg_addr;

	u16	reg_ctx_type;

	u16	reg_arr_size;

	u32	msr_addr;

	u64	mm_reg_addr;

};

/* ARM Processor Error Section */

/* ARM Processor Error Section, UEFI v2.7 sec N.2.4.4 */

struct cper_sec_proc_arm {

	__u32	validation_bits;

	__u16	err_info_num;		/* Number of Processor Error Info */

	__u16	context_info_num;	/* Number of Processor Context Info Records*/

	__u32	section_length;

	__u8	affinity_level;

	__u8	reserved[3];		/* must be zero */

	__u64	mpidr;

	__u64	midr;

	__u32	running_state;		/* Bit 0 set - Processor running. PSCI = 0 */

	__u32	psci_state;

	u32	validation_bits;

	u16	err_info_num;		/* Number of Processor Error Info */

	u16	context_info_num;	/* Number of Processor Context Info Records*/

	u32	section_length;

	u8	affinity_level;

	u8	reserved[3];		/* must be zero */

	u64	mpidr;

	u64	midr;

	u32	running_state;		/* Bit 0 set - Processor running. PSCI = 0 */

	u32	psci_state;

};

/* ARM Processor Error Information Structure */

/* ARM Processor Error Information Structure, UEFI v2.7 sec N.2.4.4.1 */

struct cper_arm_err_info {

	__u8	version;

	__u8	length;

	__u16	validation_bits;

	__u8	type;

	__u16	multiple_error;

	__u8	flags;

	__u64	error_info;

	__u64	virt_fault_addr;

	__u64	physical_fault_addr;

	u8	version;

	u8	length;

	u16	validation_bits;

	u8	type;

	u16	multiple_error;

	u8	flags;

	u64	error_info;

	u64	virt_fault_addr;

	u64	physical_fault_addr;

};

/* ARM Processor Context Information Structure */

/* ARM Processor Context Information Structure, UEFI v2.7 sec N.2.4.4.2 */

struct cper_arm_ctx_info {

	__u16	version;

	__u16	type;

	__u32	size;

	u16	version;

	u16	type;

	u32	size;

};

/* Old Memory Error Section UEFI 2.1, 2.2 */

/* Old Memory Error Section, UEFI v2.1, v2.2 */

struct cper_sec_mem_err_old {

	__u64	validation_bits;

	__u64	error_status;

	__u64	physical_addr;

	__u64	physical_addr_mask;

	__u16	node;

	__u16	card;

	__u16	module;