Commit c799a777 authored by Aidan MacDonald's avatar Aidan MacDonald Committed by Stephen Boyd
Browse files

clk: ingenic: Add .set_rate_hook() for PLL clocks 



The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.

Signed-off-by: default avatarAidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-4-aidanmacdonald.0x0@gmail.com


Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent d84bf9d6

drivers/clk/ingenic/cgu.c

+3 −0
Original line number Diff line number Diff line
@@ -232,6 +232,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, 


	writel(ctl, cgu->base + pll_info->reg);



	if (pll_info->set_rate_hook)

		pll_info->set_rate_hook(pll_info, rate, parent_rate);



	/* If the PLL is enabled, verify that it's stable */

	if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))

		ret = ingenic_pll_check_stable(cgu, pll_info);

drivers/clk/ingenic/cgu.h

+4 −0
Original line number Diff line number Diff line
@@ -46,6 +46,8 @@ 
 *		-1 if there is no enable bit (ie, the PLL is always on)

 * @stable_bit: the index of the stable bit in the PLL control register, or

 *		-1 if there is no stable bit

 * @set_rate_hook: hook called immediately after updating the CGU register,

 *		   before releasing the spinlock

 */

struct ingenic_cgu_pll_info {

	unsigned reg;
@@ -61,6 +63,8 @@ struct ingenic_cgu_pll_info { 
	void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,

			    unsigned long rate, unsigned long parent_rate,

			    unsigned int *m, unsigned int *n, unsigned int *od);

	void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,

			      unsigned long rate, unsigned long parent_rate);

};



/**