Commit c779bc1a authored by Peter Zijlstra's avatar Peter Zijlstra Committed by Borislav Petkov
Browse files

x86/bugs: Optimize SPEC_CTRL MSR writes 



When changing SPEC_CTRL for user control, the WRMSR can be delayed
until return-to-user when KERNEL_IBRS has been enabled.

This avoids an MSR write during context switch.

Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarJosh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 2dbb887e

arch/x86/include/asm/nospec-branch.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -253,7 +253,7 @@ static inline void indirect_branch_prediction_barrier(void) 




/* The Intel SPEC CTRL MSR base value cache */

/* The Intel SPEC CTRL MSR base value cache */

extern u64 x86_spec_ctrl_base;

extern u64 x86_spec_ctrl_base;

extern void write_spec_ctrl_current(u64 val);

extern void write_spec_ctrl_current(u64 val, bool force);





/*

/*

 * With retpoline, we must use IBRS to restrict branch prediction

 * With retpoline, we must use IBRS to restrict branch prediction

arch/x86/kernel/cpu/bugs.c

+12 −6
Original line number Original line Diff line number Diff line
@@ -63,12 +63,18 @@ static DEFINE_MUTEX(spec_ctrl_mutex); 
 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ

 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ

 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().

 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().

 */

 */

void write_spec_ctrl_current(u64 val)

void write_spec_ctrl_current(u64 val, bool force)

{

{

	if (this_cpu_read(x86_spec_ctrl_current) == val)

	if (this_cpu_read(x86_spec_ctrl_current) == val)

		return;

		return;





	this_cpu_write(x86_spec_ctrl_current, val);

	this_cpu_write(x86_spec_ctrl_current, val);



	/*

	 * When KERNEL_IBRS this MSR is written on return-to-user, unless

	 * forced the update can be delayed until that time.

	 */

	if (force || !cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))

		wrmsrl(MSR_IA32_SPEC_CTRL, val);

		wrmsrl(MSR_IA32_SPEC_CTRL, val);

}

}
@@ -1297,7 +1303,7 @@ static void __init spectre_v2_select_mitigation(void) 
	if (spectre_v2_in_eibrs_mode(mode)) {

	if (spectre_v2_in_eibrs_mode(mode)) {

		/* Force it so VMEXIT will restore correctly */

		/* Force it so VMEXIT will restore correctly */

		x86_spec_ctrl_base |= SPEC_CTRL_IBRS;

		x86_spec_ctrl_base |= SPEC_CTRL_IBRS;

		write_spec_ctrl_current(x86_spec_ctrl_base);

		write_spec_ctrl_current(x86_spec_ctrl_base, true);

	}

	}





	switch (mode) {

	switch (mode) {
@@ -1352,7 +1358,7 @@ static void __init spectre_v2_select_mitigation(void) 




static void update_stibp_msr(void * __unused)

static void update_stibp_msr(void * __unused)

{

{

	write_spec_ctrl_current(x86_spec_ctrl_base);

	write_spec_ctrl_current(x86_spec_ctrl_base, true);

}

}





/* Update x86_spec_ctrl_base in case SMT state changed. */

/* Update x86_spec_ctrl_base in case SMT state changed. */
@@ -1595,7 +1601,7 @@ static enum ssb_mitigation __init __ssb_select_mitigation(void) 
			x86_amd_ssb_disable();

			x86_amd_ssb_disable();

		} else {

		} else {

			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;

			x86_spec_ctrl_base |= SPEC_CTRL_SSBD;

			write_spec_ctrl_current(x86_spec_ctrl_base);

			write_spec_ctrl_current(x86_spec_ctrl_base, true);

		}

		}

	}

	}
@@ -1846,7 +1852,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) 
void x86_spec_ctrl_setup_ap(void)

void x86_spec_ctrl_setup_ap(void)

{

{

	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))

	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))

		write_spec_ctrl_current(x86_spec_ctrl_base);

		write_spec_ctrl_current(x86_spec_ctrl_base, true);





	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)

	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)

		x86_amd_ssb_disable();

		x86_amd_ssb_disable();

arch/x86/kernel/process.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -600,7 +600,7 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, 
	}

	}





	if (updmsr)

	if (updmsr)

		write_spec_ctrl_current(msr);

		write_spec_ctrl_current(msr, false);

}

}





static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)

static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)