Commit c7289b1c authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Enable SMMU support on Tegra194 



Add the device tree node for the dual-SMMU found on Tegra194 and hook up
peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent b966d2db

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+86 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_EQOS>;

			status = "disabled";



			snps,write-requests = <1>;
@@ -733,6 +734,7 @@ 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC1>;

			nvidia,pad-autocal-pull-up-offset-3v3-timeout =

									<0x07>;

			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@ 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC3>;

			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;

			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;

			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@ 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC4>;

			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@ 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_HDA>;

			status = "disabled";

		};
@@ -1300,6 +1305,84 @@ 
			interrupt-controller;

		};



		smmu: iommu@12000000 {

			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";

			reg = <0x12000000 0x800000>,

			      <0x11000000 0x800000>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			stream-match-mask = <0x7f80>;

			#global-interrupts = <2>;

			#iommu-cells = <1>;



			nvidia,memory-controller = <&mc>;

			status = "okay";

		};



		host1x@13e00000 {

			compatible = "nvidia,tegra194-host1x";

			reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@ 
			ranges = <0x15000000 0x15000000 0x01000000>;

			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;

			interconnect-names = "dma-mem";

			iommus = <&smmu TEGRA194_SID_HOST1X>;



			display-hub@15200000 {

				compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@ 
				interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,

						<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;

				interconnect-names = "dma-mem", "write";

				iommus = <&smmu TEGRA194_SID_VIC>;

			};



			dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@ 
				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,

				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;

		interconnect-names = "read", "write", "dma-mem", "dma-write";

		iommus = <&smmu TEGRA194_SID_BPMP>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";