Commit c7020e1b authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull PCI updates from Bjorn Helgaas:
 "Enumeration:

   - Squash portdrv_{core,pci}.c into portdrv.c to ease maintenance and
     make more things static.

   - Make portdrv bind to Switch Ports that have AER. Previously, if
     these Ports lacked MSI/MSI-X, portdrv failed to bind, which meant
     the Ports couldn't be suspended to low-power states. AER on these
     Ports doesn't use interrupts, and the AER driver doesn't need to
     claim them.

   - Assign PCI domain IDs using ida_alloc(), which makes host bridge
     add/remove work better.

  Resource management:

   - To work better with recent BIOSes that use EfiMemoryMappedIO for
     PCI host bridge apertures, remove those regions from the E820 map
     (E820 entries normally prevent us from allocating BARs). In v5.19,
     we added some quirks to disable E820 checking, but that's not very
     maintainable. EfiMemoryMappedIO means the OS needs to map the
     region for use by EFI runtime services; it shouldn't prevent OS
     from using it.

  PCIe native device hotplug:

   - Build pciehp by default if USB4 is enabled, since Thunderbolt/USB4
     PCIe tunneling depends on native PCIe hotplug.

   - Enable Command Completed Interrupt only if supported to avoid user
     confusion from lspci output that says this is enabled but not
     supported.

   - Prevent pciehp from binding to Switch Upstream Ports; this happened
     because of interaction with acpiphp and caused devices below the
     Upstream Port to disappear.

  Power management:

   - Convert AGP drivers to generic power management. We hope to remove
     legacy power management from the PCI core eventually.

  Virtualization:

   - Fix pci_device_is_present(), which previously always returned
     "false" for VFs, causing virtio hangs when unbinding the driver.

  Miscellaneous:

   - Convert drivers to gpiod API to prepare for dropping some legacy
     code.

   - Fix DOE fencepost error for the maximum data object length.

  Baikal-T1 PCIe controller driver:

   - Add driver and DT bindings.

  Broadcom STB PCIe controller driver:

   - Enable Multi-MSI.

   - Delay 100ms after PERST# deassert to allow power and clocks to
     stabilize.

   - Configure Read Completion Boundary to 64 bytes.

  Freescale i.MX6 PCIe controller driver:

   - Initialize PHY before deasserting core reset to fix a regression in
     v6.0 on boards where the PHY provides the reference.

   - Fix imx6sx and imx8mq clock names in DT schema.

  Intel VMD host bridge driver:

   - Fix Secondary Bus Reset on VMD bridges, which allows reset of NVMe
     SSDs in VT-d pass-through scenarios.

   - Disable MSI remapping, which gets re-enabled by firmware during
     suspend/resume.

  MediaTek PCIe Gen3 controller driver:

   - Add MT7986 and MT8195 support.

  Qualcomm PCIe controller driver:

   - Add SC8280XP/SA8540P basic interconnect support.

  Rockchip DesignWare PCIe controller driver:

   - Base DT schema on common Synopsys schema.

  Synopsys DesignWare PCIe core:

   - Collect DT items shared between Root Port and Endpoint (PERST GPIO,
     PHY info, clocks, resets, link speed, number of lanes, number of
     iATU windows, interrupt info, etc) to snps,dw-pcie-common.yaml.

   - Add dma-ranges support for Root Ports and Endpoints.

   - Consolidate DT resource retrieval for "dbi", "dbi2", "atu", etc. to
     reduce code duplication.

   - Add generic names for clocks and resets to encourage more
     consistent naming across drivers using DesignWare IP.

   - Stop advertising PTM Responder role for Endpoints, which aren't
     allowed to be responders.

  TI J721E PCIe driver:

   - Add j721s2 host mode ID to DT schema.

   - Add interrupt properties to DT schema.

  Toshiba Visconti PCIe controller driver:

   - Fix interrupts array max constraints in DT schema"

* tag 'pci-v6.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (95 commits)
  x86/PCI: Use pr_info() when possible
  x86/PCI: Fix log message typo
  x86/PCI: Tidy E820 removal messages
  PCI: Skip allocate_resource() if too little space available
  efi/x86: Remove EfiMemoryMappedIO from E820 map
  PCI/portdrv: Allow AER service only for Root Ports & RCECs
  PCI: xilinx-nwl: Fix coding style violations
  PCI: mvebu: Switch to using gpiod API
  PCI: pciehp: Enable Command Completed Interrupt only if supported
  PCI: aardvark: Switch to using devm_gpiod_get_optional()
  dt-bindings: PCI: mediatek-gen3: add support for mt7986
  dt-bindings: PCI: mediatek-gen3: add SoC based clock config
  dt-bindings: PCI: qcom: Allow 'dma-coherent' property
  PCI: mt7621: Add sentinel to quirks table
  PCI: vmd: Fix secondary bus reset for Intel bridges
  PCI: endpoint: pci-epf-vntb: Fix sparse ntb->reg build warning
  PCI: endpoint: pci-epf-vntb: Fix sparse build warning for epf_db
  PCI: endpoint: pci-epf-vntb: Replace hardcoded 4 with sizeof(u32)
  PCI: endpoint: pci-epf-vntb: Remove unused epf_db_phy struct member
  PCI: endpoint: pci-epf-vntb: Fix call pci_epc_mem_free_addr() in error path
  ...
parents a0a6c76c f826afe5
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Baikal-T1 PCIe Root Port Controller

maintainers:
  - Serge Semin <fancer.lancer@gmail.com>

description:
  Embedded into Baikal-T1 SoC Root Complex controller with a single port
  activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
  to have just a single Root Port function and is capable of establishing the
  link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
  control module, so the proper interface initialization is supposed to be
  performed by software. There four in- and four outbound iATU regions
  which can be used to emit all required TLP types on the PCIe bus.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    const: baikal,bt1-pcie

  reg:
    description:
      DBI, DBI2 and at least 4KB outbound iATU-capable region for the
      peripheral devices CFG-space access.
    maxItems: 3

  reg-names:
    items:
      - const: dbi
      - const: dbi2
      - const: config

  interrupts:
    description:
      MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
      request and eight Read/Write eDMA IRQ lines are available.
    maxItems: 14

  interrupt-names:
    items:
      - const: dma0
      - const: dma1
      - const: dma2
      - const: dma3
      - const: dma4
      - const: dma5
      - const: dma6
      - const: dma7
      - const: msi
      - const: aer
      - const: pme
      - const: hp
      - const: bw_mg
      - const: l_eq

  clocks:
    description:
      DBI (attached to the APB bus), AXI-bus master and slave interfaces
      are fed up by the dedicated application clocks. A common reference
      clock signal is supposed to be attached to the corresponding Ref-pad
      of the SoC. It will be redistributed amongst the controller core
      sub-modules (pipe, core, aux, etc).
    maxItems: 4

  clock-names:
    items:
      - const: dbi
      - const: mstr
      - const: slv
      - const: ref

  resets:
    description:
      A comprehensive controller reset logic is supposed to be implemented
      by software, so almost all the possible application and core reset
      signals are exposed via the system CCU module.
    maxItems: 9

  reset-names:
    items:
      - const: mstr
      - const: slv
      - const: pwr
      - const: hot
      - const: phy
      - const: core
      - const: pipe
      - const: sticky
      - const: non-sticky

  baikal,bt1-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the Baikal-T1 System Controller DT node. It's required to
      access some additional PM, Reset-related and LTSSM signals.

  num-lanes:
    maximum: 4

  max-link-speed:
    maximum: 3

required:
  - compatible
  - reg
  - reg-names
  - interrupts
  - interrupt-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/mips-gic.h>
    #include <dt-bindings/gpio/gpio.h>

    pcie@1f052000 {
      compatible = "baikal,bt1-pcie";
      device_type = "pci";
      reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
      reg-names = "dbi", "dbi2", "config";
      #address-cells = <3>;
      #size-cells = <2>;
      ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
               <0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
      bus-range = <0x0 0xff>;

      interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
                   <GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-names = "dma0", "dma1", "dma2", "dma3",
                        "dma4", "dma5", "dma6", "dma7",
                        "msi", "aer", "pme", "hp", "bw_mg",
                        "l_eq";

      clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
      clock-names = "dbi", "mstr", "slv", "ref";

      resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
               <&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
               <&ccu_sys 9>;
      reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
                    "sticky", "non-sticky";

      reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;

      num-lanes = <4>;
      max-link-speed = <3>;
    };
...
+42 −4
Original line number Diff line number Diff line
@@ -14,9 +14,6 @@ description: |+
  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
  and thus inherits all the common properties defined in snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
    enum:
@@ -61,7 +58,7 @@ properties:
      - const: pcie
      - const: pcie_bus
      - const: pcie_phy
      - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
      - enum: [ pcie_inbound_axi, pcie_aux ]

  num-lanes:
    const: 1
@@ -175,6 +172,47 @@ required:
  - clocks
  - clock-names

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx6sx-pcie
    then:
      properties:
        clock-names:
          items:
            - {}
            - {}
            - {}
            - const: pcie_inbound_axi
  - if:
      properties:
        compatible:
          contains:
            const: fsl,imx8mq-pcie
    then:
      properties:
        clock-names:
          items:
            - {}
            - {}
            - {}
            - const: pcie_aux
  - if:
      properties:
        compatible:
          not:
            contains:
              enum:
                - fsl,imx6sx-pcie
                - fsl,imx8mq-pcie
    then:
      properties:
        clock-names:
          maxItems: 3

unevaluatedProperties: false

examples:
+63 −14
Original line number Diff line number Diff line
@@ -43,14 +43,12 @@ description: |+
  each set has its own address for MSI message, and supports 32 MSI vectors
  to generate interrupt.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt7986-pcie
              - mediatek,mt8188-pcie
              - mediatek,mt8195-pcie
          - const: mediatek,mt8192-pcie
@@ -70,29 +68,29 @@ properties:
    minItems: 1
    maxItems: 8

  iommu-map:
    maxItems: 1

  iommu-map-mask:
    const: 0

  resets:
    minItems: 1
    maxItems: 2

  reset-names:
    minItems: 1
    maxItems: 2
    items:
      - const: phy
      - const: mac
      enum: [ phy, mac ]

  clocks:
    minItems: 4
    maxItems: 6

  clock-names:
    items:
      - const: pl_250m
      - const: tl_26m
      - const: tl_96m
      - const: tl_32k
      - const: peri_26m
      - enum:
          - top_133m        # for MT8192
          - peri_mem        # for MT8188/MT8195
    minItems: 4
    maxItems: 6

  assigned-clocks:
    maxItems: 1
@@ -107,6 +105,9 @@ properties:
    items:
      - const: pcie-phy

  power-domains:
    maxItems: 1

  '#interrupt-cells':
    const: 1

@@ -138,6 +139,54 @@ required:
  - '#interrupt-cells'
  - interrupt-controller

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - if:
      properties:
        compatible:
          const: mediatek,mt8192-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: tl_96m
            - const: tl_32k
            - const: peri_26m
            - const: top_133m
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8188-pcie
              - mediatek,mt8195-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: tl_96m
            - const: tl_32k
            - const: peri_26m
            - const: peri_mem
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt7986-pcie
    then:
      properties:
        clock-names:
          items:
            - const: pl_250m
            - const: tl_26m
            - const: peri_26m
            - const: top_133m

unevaluatedProperties: false

examples:
+22 −0
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@@ -62,6 +62,16 @@ properties:
    minItems: 3
    maxItems: 13

  dma-coherent: true

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: pcie-mem
      - const: cpu-pcie

  resets:
    minItems: 1
    maxItems: 12
@@ -631,6 +641,18 @@ allOf:
          items:
            - const: pci # PCIe core reset

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pcie-sa8540p
              - qcom,pcie-sc8280xp
    then:
      required:
        - interconnects
        - interconnect-names

  - if:
      not:
        properties:
+2 −2
Original line number Diff line number Diff line
@@ -14,10 +14,10 @@ maintainers:
description: |+
  RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
  PCIe IP and thus inherits all the common properties defined in
  designware-pcie.txt.
  snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/pci-bus.yaml#
  - $ref: /schemas/pci/snps,dw-pcie.yaml#

properties:
  compatible:
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