Commit c6e9c044 authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update events and metrics for cascadelakex 

Update to v16, the metrics are based on TMA 4.4 full, update events and add
new metrics “UNCORE_FREQ” for cascadelakex.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py



to download and generate the latest events and metrics. Manually copy
the cascadelakex files into perf.

Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Tested-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220812085239.3089231-4-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent e349fa6c

tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json

+6 −0
Original line number Diff line number Diff line
@@ -715,6 +715,12 @@ 
        "MetricGroup": "SoC",

        "MetricName": "Socket_CLKS"

    },

    {

        "BriefDescription": "Uncore frequency per die [GHZ]",

        "MetricExpr": "cha_0@event\\=0x0@ / #num_dies / duration_time / 1000000000",

        "MetricGroup": "SoC",

        "MetricName": "UNCORE_FREQ"

    },

    {

        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",

        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",

tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json

+4302 −122

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tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json

+21691 −1471

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tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json

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[

    {

        "BriefDescription": "pclk Cycles",

        "Counter": "0,1,2,3",

        "EventName": "UNC_P_CLOCKTICKS",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES",

        "Counter": "0,1,2,3",

        "EventCode": "0x60",

        "EventName": "UNC_P_CORE_TRANSITION_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "UNC_P_DEMOTIONS",

        "Counter": "0,1,2,3",

        "EventCode": "0x30",

        "EventName": "UNC_P_DEMOTIONS",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Phase Shed 0 Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x75",

        "EventName": "UNC_P_FIVR_PS_PS0_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Phase Shed 1 Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x76",

        "EventName": "UNC_P_FIVR_PS_PS1_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Phase Shed 2 Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x77",

        "EventName": "UNC_P_FIVR_PS_PS2_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Phase Shed 3 Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x78",

        "EventName": "UNC_P_FIVR_PS_PS3_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Thermal Strongest Upper Limit Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x4",

        "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Power Strongest Upper Limit Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x5",

        "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "IO P Limit Strongest Lower Limit Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x73",

        "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Cycles spent changing Frequency",

        "Counter": "0,1,2,3",

        "EventCode": "0x74",

        "EventName": "UNC_P_FREQ_TRANS_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES",

        "Counter": "0,1,2,3",

        "EventCode": "0x6",

        "EventName": "UNC_P_MCP_PROCHOT_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Memory Phase Shedding Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x2F",

        "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Package C State Residency - C0",

        "Counter": "0,1,2,3",

        "EventCode": "0x2A",

        "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Package C State Residency - C2E",

        "Counter": "0,1,2,3",

        "EventCode": "0x2B",

        "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Package C State Residency - C3",

        "Counter": "0,1,2,3",

        "EventCode": "0x2C",

        "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Package C State Residency - C6",

        "Counter": "0,1,2,3",

        "EventCode": "0x2D",

        "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES",

        "Counter": "0,1,2,3",

        "EventCode": "0x7",

        "EventName": "UNC_P_PMAX_THROTTLED_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Number of cores in C-State; C0 and C1",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Number of cores in C-State; C3",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Number of cores in C-State; C6 and C7",

        "Counter": "0,1,2,3",

        "EventCode": "0x80",

        "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "External Prochot",

        "Counter": "0,1,2,3",

        "EventCode": "0xA",

        "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Internal Prochot",

        "Counter": "0,1,2,3",

        "EventCode": "0x9",

        "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "Total Core C State Transition Cycles",

        "Counter": "0,1,2,3",

        "EventCode": "0x72",

        "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    },

    {

        "BriefDescription": "VR Hot",

        "Counter": "0,1,2,3",

        "EventCode": "0x42",

        "EventName": "UNC_P_VR_HOT_CYCLES",

        "PerPkg": "1",

        "Unit": "PCU"

    }

]