Commit c6e7deb0 authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy
Browse files

drm/i915: Introduce new Tile 4 format 



This tiling layout uses 4KB tiles in a row-major layout. It has the same
shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
only differs from Tile Y at the 256B granularity in between. At this
granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
of 64B x 8 rows.

Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Acked-by: default avatarNanley Chery <nanley.g.chery@intel.com>
Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220118115544.15116-2-stanislav.lisovskiy@intel.com
parent 30424eba

include/uapi/drm/drm_fourcc.h

+11 −0
Original line number Diff line number Diff line
@@ -572,6 +572,17 @@ extern "C" { 
 */

#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)



/*

 * Intel Tile 4 layout

 *

 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same

 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It

 * only differs from Tile Y at the 256B granularity in between. At this

 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape

 * of 64B x 8 rows.

 */

#define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)



/*

 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks

 *