Commit c6e38067 authored by Anshuman Gupta's avatar Anshuman Gupta Committed by Matt Roper
Browse files

drm/i915/dg2: Add Wa_14015795083 



i915 must disable Render DOP clock gating globally.

v2:
- Addressed cosmetic review comments.

Bspec: 52621
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220607104542.8559-1-anshuman.gupta@intel.com
parent 34b68c17

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -631,6 +631,7 @@ 


#define GEN7_MISCCPCTL				_MMIO(0x9424)

#define   GEN7_DOP_CLOCK_GATE_ENABLE		(1 << 0)

#define   GEN12_DOP_CLOCK_GATE_RENDER_ENABLE	REG_BIT(1)

#define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE	(1 << 2)

#define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE	(1 << 4)

#define   GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE	(1 << 6)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+3 −0
Original line number Diff line number Diff line
@@ -1486,6 +1486,9 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
	 * performance guide section.

	 */

	wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);



	/* Wa_14015795083 */

	wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);

}



static void