net: z85230: fix the comments style issue

// SPDX-License-Identifier: GPL-2.0-or-later

/*

 *

 *	(c) Copyright 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>

/*	(c) Copyright 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>

 *	(c) Copyright 2000, 2001 Red Hat Inc

 *

 *	Development of this driver was funded by Equiinet Ltd

	z8530_write_port(c->dataio, val);

}

/*

 *	Register loading parameters for a dead port

/*	Register loading parameters for a dead port

 */

u8 z8530_dead_port[]=

};

EXPORT_SYMBOL(z8530_dead_port);

/*

 *	Register loading parameters for currently supported circuit types

/*	Register loading parameters for currently supported circuit types

 */

/*

 *	Data clocked by telco end. This is the correct data for the UK

/*	Data clocked by telco end. This is the correct data for the UK

 *	"kilostream" service, and most other similar services.

 */

};

EXPORT_SYMBOL(z8530_hdlc_kilostream);

/*

 *	As above but for enhanced chips.

/*	As above but for enhanced chips.

 */

u8 z8530_hdlc_kilostream_85230[]=

		ch=read_zsdata(c);

		stat=read_zsreg(c, R1);

		/*

		 *	Overrun ?

		/*	Overrun ?

		 */

		if(c->count < c->max)

		{

		if(stat&END_FR)

		{

			/*

			 *	Error ?

			/*	Error ?

			 */

			if(stat&(Rx_OVR|CRC_ERR))

			{

			}

			else

			{

				/*

				 *	Drop the lock for RX processing, or

				/*	Drop the lock for RX processing, or

		 		 *	there are deadlocks

		 		 */

				z8530_rx_done(c);

			}

		}

	}

	/*

	 *	Clear irq

	/*	Clear irq

	 */

	write_zsctrl(c, ERR_RES);

	write_zsctrl(c, RES_H_IUS);

		if(!(read_zsreg(c, R0)&4))

			return;

		c->txcount--;

		/*

		 *	Shovel out the byte

		/*	Shovel out the byte

		 */

		write_zsreg(c, R8, *c->tx_ptr++);

		write_zsctrl(c, RES_H_IUS);

		}

	}

	/*

	 *	End of frame TX - fire another one

	/*	End of frame TX - fire another one

	 */

	write_zsctrl(c, RES_Tx_P);

static void z8530_rx_clear(struct z8530_channel *c)

{

	/*

	 *	Data and status bytes

	/*	Data and status bytes

	 */

	u8 stat;

	if(stat&END_FR)

		write_zsctrl(c, RES_Rx_CRC);

	/*

	 *	Clear irq

	/*	Clear irq

	 */

	write_zsctrl(c, ERR_RES);

	write_zsctrl(c, RES_H_IUS);

		if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))

			break;

		/* This holds the IRQ status. On the 8530 you must read it from chan 

		   A even though it applies to the whole chip */

		/* This holds the IRQ status. On the 8530 you must read it

		 * from chan A even though it applies to the whole chip

		 */

		/* Now walk the chip and see what it is wanting - it may be

		   an IRQ for someone else remember */

		 * an IRQ for someone else remember

		 */

		irqs=dev->chanA.irqs;

	c->count = 0;

	c->skb = NULL;

	c->skb2 = NULL;

	/*

	 *	Load the DMA interfaces up

	/*	Load the DMA interfaces up

	 */

	c->rxdma_on = 0;

	c->txdma_on = 0;

	/*

	 *	Allocate the DMA flip buffers. Limit by page size.

	/*	Allocate the DMA flip buffers. Limit by page size.

	 *	Everyone runs 1500 mtu or less on wan links so this

	 *	should be fine.

	 */

	c->dma_num=0;

	c->dma_ready=1;

	/*

	 *	Enable DMA control mode

	/*	Enable DMA control mode

	 */

	spin_lock_irqsave(c->lock, cflags);

	/*

	 *	TX DMA via DIR/REQ

	/*	TX DMA via DIR/REQ

	 */

	c->regs[R14]|= DTRREQ;

	c->regs[R1]&= ~TxINT_ENAB;

	write_zsreg(c, R1, c->regs[R1]);

	/*

	 *	RX DMA via W/Req

	/*	RX DMA via W/Req

	 */	 

	c->regs[R1]|= WT_FN_RDYFN;

	c->regs[R1]|= WT_RDY_ENAB;

	write_zsreg(c, R1, c->regs[R1]);            

	/*

	 *	DMA interrupts

	/*	DMA interrupts

	 */

	/*

	 *	Set up the DMA configuration

	/*	Set up the DMA configuration

	 */	

	dflags=claim_dma_lock();

	release_dma_lock(dflags);

	/*

	 *	Select the DMA interrupt handlers

	/*	Select the DMA interrupt handlers

	 */

	c->rxdma_on = 1;

	c->max = 0;

	c->sync = 0;

	/*

	 *	Disable the PC DMA channels

	/*	Disable the PC DMA channels

	 */

	flags=claim_dma_lock(); 

	spin_lock_irqsave(c->lock, flags);

	/*

	 *	Disable DMA control mode

	/*	Disable DMA control mode

	 */

	c->regs[R1]&= ~WT_RDY_ENAB;

	c->skb = NULL;

	c->skb2 = NULL;

	/*

	 *	Allocate the DMA flip buffers. Limit by page size.

	/*	Allocate the DMA flip buffers. Limit by page size.

	 *	Everyone runs 1500 mtu or less on wan links so this

	 *	should be fine.

	 */

	spin_lock_irqsave(c->lock, cflags);

	/*

	 *	Load the PIO receive ring

	/*	Load the PIO receive ring

	 */

	z8530_rx_done(c);

	z8530_rx_done(c);

	/*

	 *	Load the DMA interfaces up

	/*	Load the DMA interfaces up

	 */

	c->rxdma_on = 0;

	c->dma_ready=1;

	c->dma_tx = 1;

	/*

	 *	Enable DMA control mode

	/*	Enable DMA control mode

	 */

	/*

	 *	TX DMA via DIR/REQ

	/*	TX DMA via DIR/REQ

	 */

	c->regs[R14]|= DTRREQ;

	write_zsreg(c, R14, c->regs[R14]);     

	c->regs[R1]&= ~TxINT_ENAB;

	write_zsreg(c, R1, c->regs[R1]);

	/*

	 *	Set up the DMA configuration

	/*	Set up the DMA configuration

	 */	

	dflags = claim_dma_lock();

	release_dma_lock(dflags);

	/*

	 *	Select the DMA interrupt handlers

	/*	Select the DMA interrupt handlers

	 */

	c->rxdma_on = 0;

	c->max = 0;

	c->sync = 0;

	/*

	 *	Disable the PC DMA channels

	/*	Disable the PC DMA channels

	 */

	dflags = claim_dma_lock();

	release_dma_lock(dflags);

	/*

	 *	Disable DMA control mode

	/*	Disable DMA control mode

	 */

	c->regs[R1]&= ~WT_RDY_ENAB;

}

EXPORT_SYMBOL(z8530_sync_txdma_close);

/*

 *	Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny

/*	Name strings for Z8530 chips. SGI claim to have a 130, Zilog deny

 *	it exists...

 */

}

EXPORT_SYMBOL(z8530_describe);

/*

 *	Locked operation part of the z8530 init code

/*	Locked operation part of the z8530 init code

 */

static inline int do_z8530_init(struct z8530_dev *dev)

{

	/* NOP the interrupt handlers first - we might get a

	   floating IRQ transition when we reset the chip */

	 * floating IRQ transition when we reset the chip

	 */

	dev->chanA.irqs=&z8530_nop;

	dev->chanB.irqs=&z8530_nop;

	dev->chanA.dcdcheck=DCD;

	dev->type=Z8530;

	/*

	 *	See the application note.

	/*	See the application note.

	 */

	write_zsreg(&dev->chanA, R15, 0x01);

	/*

	 *	If we can set the low bit of R15 then

	/*	If we can set the low bit of R15 then

	 *	the chip is enhanced.

	 */

			dev->type = Z85C30;	/* Z85C30, 1 byte FIFO */

	}

	/*

	 *	The code assumes R7' and friends are

	/*	The code assumes R7' and friends are

	 *	off. Use write_zsext() for these and keep

	 *	this bit clear.

	 */

	write_zsreg(&dev->chanA, R15, 0);

	/*

	 *	At this point it looks like the chip is behaving

	/*	At this point it looks like the chip is behaving

	 */

	memcpy(dev->chanA.regs, reg_init, 16);

		{

			flags=claim_dma_lock();

			disable_dma(c->txdma);

			/*

			 *	Check if we crapped out.

			/*	Check if we crapped out.

			 */

			if (get_dma_residue(c->txdma))

			{

		if(c->dma_tx)

		{

			/*

			 *	FIXME. DMA is broken for the original 8530,

			/*	FIXME. DMA is broken for the original 8530,

			 *	on the older parts we need to set a flag and

			 *	wait for a further TX interrupt to fire this

			 *	stage off	

			flags=claim_dma_lock();

			disable_dma(c->txdma);

			/*

			 *	These two are needed by the 8530/85C30

			/*	These two are needed by the 8530/85C30

			 *	and must be issued when idling.

			 */

			}

		}

	}

	/*

	 *	Since we emptied tx_skb we can ask for more

	/*	Since we emptied tx_skb we can ask for more

	 */

	netif_wake_queue(c->netdevice);

}

	struct sk_buff *skb;

	int ct;

	/*

	 *	Is our receive engine in DMA mode

	/*	Is our receive engine in DMA mode

	 */

	if(c->rxdma_on)

	{

		/*

		 *	Save the ready state and the buffer currently

		/*	Save the ready state and the buffer currently

		 *	being used as the DMA target

		 */

		int ready=c->dma_ready;

		unsigned char *rxb=c->rx_buf[c->dma_num];

		unsigned long flags;

		/*

		 *	Complete this DMA. Necessary to find the length

		/*	Complete this DMA. Necessary to find the length

		 */		

		flags=claim_dma_lock();

			ct=2;	/* Shit happens.. */

		c->dma_ready=0;

		/*

		 *	Normal case: the other slot is free, start the next DMA

		/*	Normal case: the other slot is free, start the next DMA

		 *	into it immediately.

		 */

			c->rxdma_on = 1;

			enable_dma(c->rxdma);

			/* Stop any frames that we missed the head of

			   from passing */

			 * from passing

			 */

			write_zsreg(c, R0, RES_Rx_CRC);

		}

		else

			/* Can't occur as we dont reenable the DMA irq until

			   after the flip is done */

			 * after the flip is done

			 */

			netdev_warn(c->netdevice, "DMA flip overrun!\n");

		release_dma_lock(flags);

		/*

		 *	Shove the old buffer into an sk_buff. We can't DMA

		/*	Shove the old buffer into an sk_buff. We can't DMA

		 *	directly into one on a PC - it might be above the 16Mb

		 *	boundary. Optimisation - we could check to see if we

		 *	can avoid the copy. Optimisation 2 - make the memcpy

		RT_LOCK;

		skb = c->skb;

		/*

		 *	The game we play for non DMA is similar. We want to

		/*	The game we play for non DMA is similar. We want to

		 *	get the controller set up for the next packet as fast

		 *	as possible. We potentially only have one byte + the

		 *	fifo length for this. Thus we want to flip to the new

		c->netdevice->stats.rx_packets++;

		c->netdevice->stats.rx_bytes += ct;

	}

	/*

	 *	If we received a frame we must now process it.

	/*	If we received a frame we must now process it.

	 */

	if (skb) {

		skb_trim(skb, ct);

		return NETDEV_TX_BUSY;

	/* PC SPECIFIC - DMA limits */

	/*

	 *	If we will DMA the transmit and its gone over the ISA bus

	/*	If we will DMA the transmit and its gone over the ISA bus

	 *	limit, then copy to the flip buffer

	 */

	if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))

	{

		/* 

		 *	Send the flip buffer, and flip the flippy bit.

		/*	Send the flip buffer, and flip the flippy bit.

		 *	We don't care which is used when just so long as

		 *	we never use the same buffer twice in a row. Since

		 *	only one buffer can be going out at a time the other

}

EXPORT_SYMBOL(z8530_queue_xmit);

/*

 *	Module support

/*	Module support

 */

static const char banner[] __initconst =

	KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";