Commit c6a3d735 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2022-06-29' of... 

Merge tag 'drm-intel-gt-next-2022-06-29' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

UAPI Changes:

- Expose per tile media freq factor in sysfs (Ashutosh Dixit, Dale B Stimson)
- Document memory residency and Flat-CCS capability of obj (Ramalingam C)
- Disable GETPARAM lookups of I915_PARAM_[SUB]SLICE_MASK on Xe_HP+ (Matt Roper)

Cross-subsystem Changes:

- Rename intel-gtt symbols (Lucas De Marchi)

Core Changes:

Driver Changes:

- Support programming the EU priority in the GuC descriptor (DG2) (Matthew Brost)
- DG2 HuC loading support (Daniele Ceraolo Spurio)
- Fix build error without CONFIG_PM (YueHaibing)
- Enable THP on Icelake and beyond (Tvrtko Ursulin)
- Only setup private tmpfs mount when needed and fix logging (Tvrtko Ursulin)
- Make __guc_reset_context aware of guilty engines (Umesh Nerlige Ramappa)
- DG2 small bar memory probing fixes (Nirmoy Das)
- Remove unnecessary GuC err capture noise (Alan Previn)
- Fix i915_gem_object_ggtt_pin_ww regression on old platforms (Maarten Lankhorst)
- Fix undefined behavior in GuC backend due to shift overflowing the constant (Borislav Petkov)
- New DG2 workarounds (Swathi Dhanavanthri, Anshuman Gupta)
- Report no hwconfig support on ADL-N (Balasubramani Vivekanandan)
- Fix error_state_read ptr + offset use (Alan Previn)
- Expose per tile media freq factor in sysfs (Ashutosh Dixit, Dale B Stimson)
- Fix memory leaks in per-gt sysfs (Ashutosh Dixit)
- Fix dma_resv fence handling in multi-batch execbuf (Nirmoy Das)
- Add extra registers to GPU error dump on Gen11+ (Stuart Summers)
- More PVC+DG2 workarounds (Matt Roper)
- Improve user experience and driver robustness under SIGINT or similar (Tvrtko Ursulin)
- Don't show engine classes not present (Tvrtko Ursulin)
- Improve on suspend / resume time with VT-d enabled (Thomas Hellström)
- Add missing else (katrinzhou)
- Don't leak lmem mapping in vma_evict (Juha-Pekka Heikkila)
- Add smem fallback allocation for dpt (Juha-Pekka Heikkila)
- Tweak the ordering in cpu_write_needs_clflush (Matthew Auld)
- Do not access rq->engine without a reference (Niranjana Vishwanathapura)
- Revert "drm/i915: Hold reference to intel_context over life of i915_request" (Niranjana Vishwanathapura)
- Don't update engine busyness stats too frequently (Alan Previn)
- Add additional steps for Wa_22011802037 for execlist backend (Umesh Nerlige Ramappa)
- Fix a lockdep warning at error capture (Nirmoy Das)

- Ponte Vecchio prep work and new blitter engines (Matt Roper, John Harrison, Lucas De Marchi)
- Read correct RP_STATE_CAP register (PVC) (Matt Roper)
- Define MOCS table for PVC (Ayaz A Siddiqui)
- Driver refactor and support Ponte Vecchio forcewake handling (Matt Roper)
- Remove additional 3D flags from PIPE_CONTROL (Ponte Vecchio) (Stuart Summers)
- XEHPSDV and PVC do not use HuC (Daniele Ceraolo Spurio)
- Extract stepping information from PCI revid (Ponte Vecchio) (Matt Roper)
- Add initial PVC workarounds (Stuart Summers)
- SSEU handling driver refactor and Ponte Vecchio support (Matt Roper)
- GuC depriv applies to PVC (Matt Roper)
- Add register steering (Ponte Vecchio) (Matt Roper)
- Add recommended MMIO setting (Ponte Vecchio) (Matt Roper)

- Move multicast register handling to a dedicated file (Matt Roper)
- Cleanup interface for MCR operations (Matt Roper)
- Extend i915_vma_pin_iomap() (CQ Tang)
- Re-do the intel-gtt split (Lucas De Marchi)
- Correct duplicated/misplaced GT register definitions (Matt Roper)
- Prefer "XEHP_" prefix for registers (Matt Roper)

- Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config (Tvrtko Ursulin)
- Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle (Tvrtko Ursulin)
- Make drop_pages() return bool (Lucas De Marchi)
- Fix CFI violation with show_dynamic_id() (Nathan Chancellor)
- Use i915_probe_error instead of drm_error in GuC code (Vinay Belgaumkar)
- Fix use of static in macro mismatch (Andi Shyti)
- Update tiled blits selftest (Bommu Krishnaiah)
- Future-proof platform checks (Matt Roper)
- Only include what's needed (Jani Nikula)
- remove accidental static from a local variable (Jani Nikula)
- Add global forcewake request to drpc (Vinay Belgaumkar)
- Fix spelling typo in comment (pengfuyuan)
- Increase timeout for live_parallel_switch selftest (Akeem G Abodunrin)
- Use non-blocking H2G for waitboost (Vinay Belgaumkar)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YrwtLM081SQUG1Dc@tursulin-desk
parents f9292174 a0696856

Documentation/gpu/i915.rst

+12 −0
Original line number Diff line number Diff line
@@ -246,6 +246,18 @@ Display State Buffer 
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c

   :internal:



GT Programming

==============



Multicast/Replicated (MCR) Registers

------------------------------------



.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c

   :doc: GT Multicast/Replicated (MCR) Register Support



.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c

   :internal:



Memory Management and Command Submission

========================================

drivers/char/agp/intel-gtt.c

+29 −29
Original line number Diff line number Diff line
@@ -744,7 +744,7 @@ static void i830_write_entry(dma_addr_t addr, unsigned int entry, 
	writel_relaxed(addr | pte_flags, intel_private.gtt + entry);

}



bool intel_enable_gtt(void)

bool intel_gmch_enable_gtt(void)

{

	u8 __iomem *reg;
@@ -787,7 +787,7 @@ bool intel_enable_gtt(void) 


	return true;

}

EXPORT_SYMBOL(intel_enable_gtt);

EXPORT_SYMBOL(intel_gmch_enable_gtt);



static int i830_setup(void)

{
@@ -821,7 +821,7 @@ static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 


static int intel_fake_agp_configure(void)

{

	if (!intel_enable_gtt())

	if (!intel_gmch_enable_gtt())

		return -EIO;



	intel_private.clear_fake_agp = true;
@@ -844,7 +844,7 @@ static bool i830_check_flags(unsigned int flags) 
	return false;

}



void intel_gtt_insert_page(dma_addr_t addr,

void intel_gmch_gtt_insert_page(dma_addr_t addr,

				unsigned int pg,

				unsigned int flags)

{
@@ -853,9 +853,9 @@ void intel_gtt_insert_page(dma_addr_t addr, 
	if (intel_private.driver->chipset_flush)

		intel_private.driver->chipset_flush();

}

EXPORT_SYMBOL(intel_gtt_insert_page);

EXPORT_SYMBOL(intel_gmch_gtt_insert_page);



void intel_gtt_insert_sg_entries(struct sg_table *st,

void intel_gmch_gtt_insert_sg_entries(struct sg_table *st,

				      unsigned int pg_start,

				      unsigned int flags)

{
@@ -879,10 +879,10 @@ void intel_gtt_insert_sg_entries(struct sg_table *st, 
	if (intel_private.driver->chipset_flush)

		intel_private.driver->chipset_flush();

}

EXPORT_SYMBOL(intel_gtt_insert_sg_entries);

EXPORT_SYMBOL(intel_gmch_gtt_insert_sg_entries);



#if IS_ENABLED(CONFIG_AGP_INTEL)

static void intel_gtt_insert_pages(unsigned int first_entry,

static void intel_gmch_gtt_insert_pages(unsigned int first_entry,

					unsigned int num_entries,

					struct page **pages,

					unsigned int flags)
@@ -905,7 +905,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, 
	if (intel_private.clear_fake_agp) {

		int start = intel_private.stolen_size / PAGE_SIZE;

		int end = intel_private.gtt_mappable_entries;

		intel_gtt_clear_range(start, end - start);

		intel_gmch_gtt_clear_range(start, end - start);

		intel_private.clear_fake_agp = false;

	}
@@ -934,11 +934,11 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, 
		if (ret != 0)

			return ret;



		intel_gtt_insert_sg_entries(&st, pg_start, type);

		intel_gmch_gtt_insert_sg_entries(&st, pg_start, type);

		mem->sg_list = st.sgl;

		mem->num_sg = st.nents;

	} else

		intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,

		intel_gmch_gtt_insert_pages(pg_start, mem->page_count, mem->pages,

					    type);



out:
@@ -949,7 +949,7 @@ static int intel_fake_agp_insert_entries(struct agp_memory *mem, 
}

#endif



void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)

void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)

{

	unsigned int i;
@@ -959,7 +959,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 
	}

	wmb();

}

EXPORT_SYMBOL(intel_gtt_clear_range);

EXPORT_SYMBOL(intel_gmch_gtt_clear_range);



#if IS_ENABLED(CONFIG_AGP_INTEL)

static int intel_fake_agp_remove_entries(struct agp_memory *mem,
@@ -968,7 +968,7 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem, 
	if (mem->page_count == 0)

		return 0;



	intel_gtt_clear_range(pg_start, mem->page_count);

	intel_gmch_gtt_clear_range(pg_start, mem->page_count);



	if (intel_private.needs_dmar) {

		intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
@@ -1431,7 +1431,7 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 
}

EXPORT_SYMBOL(intel_gmch_probe);



void intel_gtt_get(u64 *gtt_total,

void intel_gmch_gtt_get(u64 *gtt_total,

			phys_addr_t *mappable_base,

			resource_size_t *mappable_end)

{
@@ -1439,14 +1439,14 @@ void intel_gtt_get(u64 *gtt_total, 
	*mappable_base = intel_private.gma_bus_addr;

	*mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;

}

EXPORT_SYMBOL(intel_gtt_get);

EXPORT_SYMBOL(intel_gmch_gtt_get);



void intel_gtt_chipset_flush(void)

void intel_gmch_gtt_flush(void)

{

	if (intel_private.driver->chipset_flush)

		intel_private.driver->chipset_flush();

}

EXPORT_SYMBOL(intel_gtt_chipset_flush);

EXPORT_SYMBOL(intel_gmch_gtt_flush);



void intel_gmch_remove(void)

{

drivers/gpu/drm/i915/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -103,6 +103,7 @@ gt-y += \ 
	gt/intel_gt_debugfs.o \

	gt/intel_gt_engines_debugfs.o \

	gt/intel_gt_irq.o \

	gt/intel_gt_mcr.o \

	gt/intel_gt_pm.o \

	gt/intel_gt_pm_debugfs.o \

	gt/intel_gt_pm_irq.o \
@@ -129,7 +130,7 @@ gt-y += \ 
	gt/shmem_utils.o \

	gt/sysfs_engines.o

# x86 intel-gtt module support

gt-$(CONFIG_X86) += gt/intel_gt_gmch.o

gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o

# autogenerated null render state

gt-y += \

	gt/gen6_renderstate.o \

drivers/gpu/drm/i915/display/intel_dpt.c

+12 −4
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
 */



#include "gem/i915_gem_domain.h"

#include "gem/i915_gem_internal.h"

#include "gt/gen8_ppgtt.h"



#include "i915_drv.h"
@@ -127,8 +128,12 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm) 
	struct i915_vma *vma;

	void __iomem *iomem;

	struct i915_gem_ww_ctx ww;

	u64 pin_flags = 0;

	int err;



	if (i915_gem_object_is_stolen(dpt->obj))

		pin_flags |= PIN_MAPPABLE;



	wakeref = intel_runtime_pm_get(&i915->runtime_pm);

	atomic_inc(&i915->gpu_error.pending_fb_pin);
@@ -138,7 +143,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm) 
			continue;



		vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0, 4096,

						  HAS_LMEM(i915) ? 0 : PIN_MAPPABLE);

						  pin_flags);

		if (IS_ERR(vma)) {

			err = PTR_ERR(vma);

			continue;
@@ -248,10 +253,13 @@ intel_dpt_create(struct intel_framebuffer *fb) 


	size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);



	if (HAS_LMEM(i915))

	dpt_obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);

	else

	if (IS_ERR(dpt_obj) && i915_ggtt_has_aperture(to_gt(i915)->ggtt))

		dpt_obj = i915_gem_object_create_stolen(i915, size);

	if (IS_ERR(dpt_obj) && !HAS_LMEM(i915)) {

		drm_dbg_kms(&i915->drm, "Allocating dpt from smem\n");

		dpt_obj = i915_gem_object_create_internal(i915, size);

	}

	if (IS_ERR(dpt_obj))

		return ERR_CAST(dpt_obj);

drivers/gpu/drm/i915/gem/i915_gem_context.c

+21 −12
Original line number Diff line number Diff line
@@ -933,6 +933,7 @@ static int set_proto_ctx_param(struct drm_i915_file_private *fpriv, 
	case I915_CONTEXT_PARAM_PERSISTENCE:

		if (args->size)

			ret = -EINVAL;

		else

			ret = proto_context_set_persistence(fpriv->dev_priv, pc,

							    args->value);

		break;
@@ -1367,7 +1368,8 @@ static struct intel_engine_cs *active_engine(struct intel_context *ce) 
	return engine;

}



static void kill_engines(struct i915_gem_engines *engines, bool ban)

static void

kill_engines(struct i915_gem_engines *engines, bool exit, bool persistent)

{

	struct i915_gem_engines_iter it;

	struct intel_context *ce;
@@ -1381,9 +1383,15 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban) 
	 */

	for_each_gem_engine(ce, engines, it) {

		struct intel_engine_cs *engine;

		bool skip = false;



		if (ban && intel_context_ban(ce, NULL))

			continue;

		if (exit)

			skip = intel_context_set_exiting(ce);

		else if (!persistent)

			skip = intel_context_exit_nonpersistent(ce, NULL);



		if (skip)

			continue; /* Already marked. */



		/*

		 * Check the current active state of this context; if we
@@ -1395,7 +1403,7 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban) 
		engine = active_engine(ce);



		/* First attempt to gracefully cancel the context */

		if (engine && !__cancel_engine(engine) && ban)

		if (engine && !__cancel_engine(engine) && (exit || !persistent))

			/*

			 * If we are unable to send a preemptive pulse to bump

			 * the context from the GPU, we have to resort to a full
@@ -1407,8 +1415,6 @@ static void kill_engines(struct i915_gem_engines *engines, bool ban) 


static void kill_context(struct i915_gem_context *ctx)

{

	bool ban = (!i915_gem_context_is_persistent(ctx) ||

		    !ctx->i915->params.enable_hangcheck);

	struct i915_gem_engines *pos, *next;



	spin_lock_irq(&ctx->stale.lock);
@@ -1421,7 +1427,8 @@ static void kill_context(struct i915_gem_context *ctx) 


		spin_unlock_irq(&ctx->stale.lock);



		kill_engines(pos, ban);

		kill_engines(pos, !ctx->i915->params.enable_hangcheck,

			     i915_gem_context_is_persistent(ctx));



		spin_lock_irq(&ctx->stale.lock);

		GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
@@ -1467,7 +1474,8 @@ static void engines_idle_release(struct i915_gem_context *ctx, 


kill:

	if (list_empty(&engines->link)) /* raced, already closed */

		kill_engines(engines, true);

		kill_engines(engines, true,

			     i915_gem_context_is_persistent(ctx));



	i915_sw_fence_commit(&engines->fence);

}
@@ -1875,6 +1883,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt, 
{

	const struct sseu_dev_info *device = &gt->info.sseu;

	struct drm_i915_private *i915 = gt->i915;

	unsigned int dev_subslice_mask = intel_sseu_get_hsw_subslices(device, 0);



	/* No zeros in any field. */

	if (!user->slice_mask || !user->subslice_mask ||
@@ -1901,7 +1910,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt, 
	if (user->slice_mask & ~device->slice_mask)

		return -EINVAL;



	if (user->subslice_mask & ~device->subslice_mask[0])

	if (user->subslice_mask & ~dev_subslice_mask)

		return -EINVAL;



	if (user->max_eus_per_subslice > device->max_eus_per_subslice)
@@ -1915,7 +1924,7 @@ i915_gem_user_to_context_sseu(struct intel_gt *gt, 
	/* Part specific restrictions. */

	if (GRAPHICS_VER(i915) == 11) {

		unsigned int hw_s = hweight8(device->slice_mask);

		unsigned int hw_ss_per_s = hweight8(device->subslice_mask[0]);

		unsigned int hw_ss_per_s = hweight8(dev_subslice_mask);

		unsigned int req_s = hweight8(context->slice_mask);

		unsigned int req_ss = hweight8(context->subslice_mask);