Commit c65b3aff authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up M/N register defines 



Use REG_GENMASK() & co. for the M/N register values. There are
also a lot of weird unused defines (eg. *_OFFSET) we can just
throw out.

Also let's mask out the unused bits during readout for good
measure. Previously we only masked out the TU_SIZE from one
of the registers, which was a bit too inconsistent for my
taste.

v2: Mention the readout masking in the commit msg  (Jani)
    Deal wth gvt

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127120219.20143-1-ville.syrjala@linux.intel.com
parent d29c9930

drivers/gpu/drm/i915/display/intel_display.c

+5 −5
Original line number Diff line number Diff line
@@ -3865,11 +3865,11 @@ static void intel_get_m_n(struct drm_i915_private *i915, 
			  i915_reg_t data_m_reg, i915_reg_t data_n_reg,

			  i915_reg_t link_m_reg, i915_reg_t link_n_reg)

{

	m_n->link_m = intel_de_read(i915, link_m_reg);

	m_n->link_n = intel_de_read(i915, link_n_reg);

	m_n->gmch_m = intel_de_read(i915, data_m_reg) & ~TU_SIZE_MASK;

	m_n->gmch_n = intel_de_read(i915, data_n_reg);

	m_n->tu = ((intel_de_read(i915, data_m_reg) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;

	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;

	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;

	m_n->gmch_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;

	m_n->gmch_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;

	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;

}



static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,

drivers/gpu/drm/i915/gvt/display.c

+2 −2
Original line number Diff line number Diff line
@@ -253,7 +253,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		 *   DP link clk 1620 MHz and non-constant_n.

		 * TODO: calculate DP link symbol clk and stream clk m/n.

		 */

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;

		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;

		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
@@ -387,7 +387,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		 *   DP link clk 1620 MHz and non-constant_n.

		 * TODO: calculate DP link symbol clk and stream clk m/n.

		 */

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);

		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;

		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;

		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;

drivers/gpu/drm/i915/i915_reg.h

+3 −19
Original line number Diff line number Diff line
@@ -5130,16 +5130,14 @@ enum { 
#define _PIPEB_DATA_M_G4X	0x71050



/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */

#define  TU_SIZE(x)             (((x) - 1) << 25) /* default size 64 */

#define  TU_SIZE_SHIFT		25

#define  TU_SIZE_MASK           (0x3f << 25)

#define  TU_SIZE_MASK		REG_GENMASK(30, 25)

#define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */



#define  DATA_LINK_M_N_MASK	(0xffffff)

#define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)

#define  DATA_LINK_N_MAX	(0x800000)



#define _PIPEA_DATA_N_G4X	0x70054

#define _PIPEB_DATA_N_G4X	0x71054

#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)



/*

 * Computing Link M and N values for the Display Port link
@@ -5154,11 +5152,8 @@ enum { 


#define _PIPEA_LINK_M_G4X	0x70060

#define _PIPEB_LINK_M_G4X	0x71060

#define   PIPEA_DP_LINK_M_MASK			(0xffffff)



#define _PIPEA_LINK_N_G4X	0x70064

#define _PIPEB_LINK_N_G4X	0x71064

#define   PIPEA_DP_LINK_N_MASK			(0xffffff)



#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)

#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
@@ -6761,24 +6756,13 @@ enum { 




#define _PIPEA_DATA_M1		0x60030

#define  PIPE_DATA_M1_OFFSET    0

#define _PIPEA_DATA_N1		0x60034

#define  PIPE_DATA_N1_OFFSET    0



#define _PIPEA_DATA_M2		0x60038

#define  PIPE_DATA_M2_OFFSET    0

#define _PIPEA_DATA_N2		0x6003c

#define  PIPE_DATA_N2_OFFSET    0



#define _PIPEA_LINK_M1		0x60040

#define  PIPE_LINK_M1_OFFSET    0

#define _PIPEA_LINK_N1		0x60044

#define  PIPE_LINK_N1_OFFSET    0



#define _PIPEA_LINK_M2		0x60048

#define  PIPE_LINK_M2_OFFSET    0

#define _PIPEA_LINK_N2		0x6004c

#define  PIPE_LINK_N2_OFFSET    0



/* PIPEB timing regs are same start from 0x61000 */