Commit c64fa77d authored by Matthew Auld's avatar Matthew Auld
Browse files

drm/i915/gtt: reduce overzealous alignment constraints for GGTT 



Currently this will enforce both 2M alignment and padding for any LMEM
pages inserted into the GGTT. However, this was only meant to be applied
to the compact-pt layout with the ppGTT. For the GGTT we can reduce the
alignment and padding to 64K.

Bspec: 45015
Fixes: 87bd701e ("drm/i915: enforce min GTT alignment for discrete cards")
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Robert Beckett <bob.beckett@collabora.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarThomas Hellström <thomas.hellstrom@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303100229.839282-1-matthew.auld@intel.com
parent e4b3ee71

drivers/gpu/drm/i915/gt/intel_gtt.c

+2 −1
Original line number Diff line number Diff line
@@ -257,7 +257,8 @@ void i915_address_space_init(struct i915_address_space *vm, int subclass) 
	memset64(vm->min_alignment, I915_GTT_MIN_ALIGNMENT,

		 ARRAY_SIZE(vm->min_alignment));



	if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915)) {

	if (HAS_64K_PAGES(vm->i915) && NEEDS_COMPACT_PT(vm->i915) &&

	    subclass == VM_CLASS_PPGTT) {

		vm->min_alignment[INTEL_MEMORY_LOCAL] = I915_GTT_PAGE_SIZE_2M;

		vm->min_alignment[INTEL_MEMORY_STOLEN_LOCAL] = I915_GTT_PAGE_SIZE_2M;

	} else if (HAS_64K_PAGES(vm->i915)) {