Commit c64daf36 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Stephen Boyd
Browse files

clk: uniphier: Add SoC-glue clock source selector support for Pro4 



Add SoC-glue clock source selector for ahci controller on UniPhier SoCs.
Currently this supports Pro4 only.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1634000035-3114-6-git-send-email-hayashi.kunihiko@socionext.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent d911ed93

drivers/clk/uniphier/clk-uniphier-core.c

+5 −0
Original line number Diff line number Diff line
@@ -210,6 +210,11 @@ static const struct of_device_id uniphier_clk_match[] = { 
		.compatible = "socionext,uniphier-nx1-peri-clock",

		.data = uniphier_pro4_peri_clk_data,

	},

	/* SoC-glue clock */

	{

		.compatible = "socionext,uniphier-pro4-sg-clock",

		.data = uniphier_pro4_sg_clk_data,

	},

	{ /* sentinel */ }

};

drivers/clk/uniphier/clk-uniphier-sys.c

+17 −0
Original line number Diff line number Diff line
@@ -330,3 +330,20 @@ const struct uniphier_clk_data uniphier_nx1_sys_clk_data[] = { 
			     "cpll/32"),

	{ /* sentinel */ }

};



const struct uniphier_clk_data uniphier_pro4_sg_clk_data[] = {

	UNIPHIER_CLK_DIV("gpll", 4),

	{

		.name = "sata-ref",

		.type = UNIPHIER_CLK_TYPE_MUX,

		.idx = 0,

		.data.mux = {

			.parent_names = { "gpll/4", "ref", },

			.num_parents = 2,

			.reg = 0x1a28,

			.masks = { 0x1, 0x1, },

			.vals  = { 0x0, 0x1, },

		},

	},

	{ /* sentinel */ }

};

drivers/clk/uniphier/clk-uniphier.h

+1 −0
Original line number Diff line number Diff line
@@ -155,5 +155,6 @@ extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[]; 
extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];

extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];

extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];

extern const struct uniphier_clk_data uniphier_pro4_sg_clk_data[];



#endif /* __CLK_UNIPHIER_H__ */