Commit c645e4b8 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/display: properly guard dc_dsc_stream_bandwidth_in_kbps 



Move the function protoype to the right header and guard
the call with CONFIG_DRM_AMD_DC_DCN as DSC is only available
with DCN.

Fixes: 8c2f14c3 ("drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations")
Reviewed-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Dillon Varone <dillon.varone@amd.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
parent 7a78e2bc

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+2 −2
Original line number Diff line number Diff line
@@ -3498,17 +3498,17 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) 
	}

}



uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);



uint32_t dc_bandwidth_in_kbps_from_timing(

	const struct dc_crtc_timing *timing)

{

	uint32_t bits_per_channel = 0;

	uint32_t kbps;



#if defined(CONFIG_DRM_AMD_DC_DCN)

	if (timing->flags.DSC) {

		return dc_dsc_stream_bandwidth_in_kbps(timing->pix_clk_100hz, timing->dsc_cfg.bits_per_pixel);

	}

#endif



	switch (timing->display_color_depth) {

	case COLOR_DEPTH_666:

drivers/gpu/drm/amd/display/dc/dc_dsc.h

+2 −0
Original line number Diff line number Diff line
@@ -88,4 +88,6 @@ void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); 


void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);



uint32_t dc_dsc_stream_bandwidth_in_kbps(uint32_t pix_clk_100hz, uint32_t bpp_x16);



#endif