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mainline inclusion from mainline-v6.9-rc1 commit 3b566b30b41401888ee0e8eb904a1e7a6693794b category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IAYOV8 CVE: NA Reference: https://github.com/torvalds/linux/commit/3b566b30b41401888ee0e8eb904a1e7a6693794b -------------------------------- commit 3b566b30b41401888ee0e8eb904a1e7a6693794b upstream. DRAM row retirement depends on model-specific information that is best done within the AMD Address Translation Library. Export a generic wrapper function for other modules to use. Add any model-specific helpers here. Signed-off-by:Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by:
Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20240214033516.1344948-2-yazen.ghannam@amd.com Signed-off-by:
Jeevan deep J <j.jeevandeep@amd.com> Signed-off-by:
PrithivishS <sprithiv@amd.com>