Commit c5d9ae26 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm 

Pull kvm fixes from Paolo Bonzini:
 "ARM:

   - Read HW interrupt pending state from the HW

  x86:

   - Don't truncate the performance event mask on AMD

   - Fix Xen runstate updates to be atomic when preempting vCPU

   - Fix for AMD AVIC interrupt injection race

   - Several other AMD fixes"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for PERF_TYPE_RAW
  KVM: x86/pmu: Don't truncate the PerfEvtSeln MSR when creating a perf event
  KVM: SVM: fix race between interrupt delivery and AVIC inhibition
  KVM: SVM: set IRR in svm_deliver_interrupt
  KVM: SVM: extract avic_ring_doorbell
  selftests: kvm: Remove absent target file
  KVM: arm64: vgic: Read HW interrupt pending state from the HW
  KVM: x86/xen: Fix runstate updates to be atomic when preempting vCPU
  KVM: x86: SVM: move avic definitions from AMD's spec to svm.h
  KVM: x86: lapic: don't touch irr_pending in kvm_apic_update_apicv when inhibiting it
  KVM: x86: nSVM: deal with L1 hypervisor that intercepts interrupts but lets L2 control them
  KVM: x86: nSVM: expose clean bit support to the guest
  KVM: x86: nSVM/nVMX: set nested_run_pending on VM entry which is a result of RSM
  KVM: x86: nSVM: mark vmcb01 as dirty when restoring SMM saved state
  KVM: x86: nSVM: fix potential NULL derefernce on nested migration
  KVM: x86: SVM: don't passthrough SMAP/SMEP/PKE bits in !NPT && !gCR0.PG case
  Revert "svm: Add warning message for AVIC IPI invalid target"
parents a254a9da 710c4765

arch/arm64/kvm/vgic/vgic-mmio.c

+2 −0
Original line number Diff line number Diff line
@@ -248,6 +248,8 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, 
						    IRQCHIP_STATE_PENDING,

						    &val);

			WARN_RATELIMIT(err, "IRQ %d", irq->host_irq);

		} else if (vgic_irq_is_mapped_level(irq)) {

			val = vgic_get_phys_line_level(irq);

		} else {

			val = irq_is_pending(irq);

		}

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -476,6 +476,7 @@ 
#define MSR_AMD64_ICIBSEXTDCTL		0xc001103c

#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */

#define MSR_AMD64_SVM_AVIC_DOORBELL	0xc001011b

#define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e

#define MSR_AMD64_SEV_ES_GHCB		0xc0010130

#define MSR_AMD64_SEV			0xc0010131

arch/x86/include/asm/svm.h

+36 −0
Original line number Diff line number Diff line
@@ -220,6 +220,42 @@ struct __attribute__ ((__packed__)) vmcb_control_area { 
#define SVM_NESTED_CTL_SEV_ENABLE	BIT(1)

#define SVM_NESTED_CTL_SEV_ES_ENABLE	BIT(2)





/* AVIC */

#define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK	(0xFF)

#define AVIC_LOGICAL_ID_ENTRY_VALID_BIT			31

#define AVIC_LOGICAL_ID_ENTRY_VALID_MASK		(1 << 31)



#define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK	(0xFFULL)

#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK	(0xFFFFFFFFFFULL << 12)

#define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK		(1ULL << 62)

#define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK		(1ULL << 63)

#define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK		(0xFF)



#define AVIC_DOORBELL_PHYSICAL_ID_MASK			(0xFF)



#define AVIC_UNACCEL_ACCESS_WRITE_MASK		1

#define AVIC_UNACCEL_ACCESS_OFFSET_MASK		0xFF0

#define AVIC_UNACCEL_ACCESS_VECTOR_MASK		0xFFFFFFFF



enum avic_ipi_failure_cause {

	AVIC_IPI_FAILURE_INVALID_INT_TYPE,

	AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,

	AVIC_IPI_FAILURE_INVALID_TARGET,

	AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,

};





/*

 * 0xff is broadcast, so the max index allowed for physical APIC ID

 * table is 0xfe.  APIC IDs above 0xff are reserved.

 */

#define AVIC_MAX_PHYSICAL_ID_COUNT	0xff



#define AVIC_HPA_MASK	~((0xFFFULL << 52) | 0xFFF)

#define VMCB_AVIC_APIC_BAR_MASK		0xFFFFFFFFFF000ULL





struct vmcb_seg {

	u16 selector;

	u16 attrib;

arch/x86/kvm/lapic.c

+6 −1
Original line number Diff line number Diff line
@@ -2306,7 +2306,12 @@ void kvm_apic_update_apicv(struct kvm_vcpu *vcpu) 
		apic->irr_pending = true;

		apic->isr_count = 1;

	} else {

		apic->irr_pending = (apic_search_irr(apic) != -1);

		/*

		 * Don't clear irr_pending, searching the IRR can race with

		 * updates from the CPU as APICv is still active from hardware's

		 * perspective.  The flag will be cleared as appropriate when

		 * KVM injects the interrupt.

		 */

		apic->isr_count = count_vectors(apic->regs + APIC_ISR);

	}

}

arch/x86/kvm/pmu.c

+4 −3
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ static void kvm_perf_overflow(struct perf_event *perf_event, 
}



static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,

				  unsigned config, bool exclude_user,

				  u64 config, bool exclude_user,

				  bool exclude_kernel, bool intr,

				  bool in_tx, bool in_tx_cp)

{
@@ -181,7 +181,8 @@ static int cmp_u64(const void *a, const void *b) 


void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)

{

	unsigned config, type = PERF_TYPE_RAW;

	u64 config;

	u32 type = PERF_TYPE_RAW;

	struct kvm *kvm = pmc->vcpu->kvm;

	struct kvm_pmu_event_filter *filter;

	bool allow_event = true;
@@ -220,7 +221,7 @@ void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel) 
	}



	if (type == PERF_TYPE_RAW)

		config = eventsel & X86_RAW_EVENT_MASK;

		config = eventsel & AMD64_RAW_EVENT_MASK;



	if (pmc->current_config == eventsel && pmc_resume_counter(pmc))

		return;