Commit c5bf8402 authored by Zhiqi Song's avatar Zhiqi Song
Browse files

crypto: hisilicon/zip - save capability registers in probe process 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7BANJ


CVE: NA

----------------------------------------------------------------------

Pre-store the valid value of the zip alg support related capability
register to a global array in hisi_zip_qm_init(), which will be
called by hisi_zip_probe(). It can reduce the number of capability
register queries and avoid obtaining incorrect values in abnormal
scenarios, such as reset failed and the memory space disabled.

Signed-off-by: default avatarZhiqi Song <songzhiqi1@huawei.com>
Signed-off-by: default avatarJiangShui Yang <yangjiangshui@h-partners.com>
parent e3e3ebd9

drivers/crypto/hisilicon/zip/zip_main.c

+44 −13
Original line number Diff line number Diff line
@@ -241,6 +241,26 @@ static struct hisi_qm_cap_info zip_basic_cap_info[] = { 
	{ZIP_CAP_MAX, 0x317c, 0, GENMASK(0, 0), 0x0, 0x0, 0x0}

};



enum zip_cap_reg_record_idx {

	ZIP_CORE_NUM_CAP_IDX,

	ZIP_CLUSTER_COMP_NUM_CAP_IDX,

	ZIP_CLUSTER_DECOMP_NUM_CAP_IDX,

	ZIP_DECOMP_ENABLE_BITMAP_IDX,

	ZIP_COMP_ENABLE_BITMAP_IDX,

	ZIP_DRV_ALG_BITMAP_IDX,

	ZIP_DEV_ALG_BITMAP_IDX,

};



static struct hisi_qm_cap_record zip_cap_reg_record[] = {

	{ZIP_CORE_NUM_CAP,		0x5},

	{ZIP_CLUSTER_COMP_NUM_CAP,	0x2},

	{ZIP_CLUSTER_DECOMP_NUM_CAP,	0x3},

	{ZIP_DECOMP_ENABLE_BITMAP,	0x1C},

	{ZIP_COMP_ENABLE_BITMAP,	0x3},

	{ZIP_DRV_ALG_BITMAP,		0xF},

	{ZIP_DEV_ALG_BITMAP,		0xFF},

};



enum {

	HZIP_COMP_CORE0,

	HZIP_COMP_CORE1,
@@ -404,7 +424,7 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) 
{

	u32 cap_val;



	cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DRV_ALG_BITMAP, qm->cap_ver);

	cap_val = zip_cap_reg_record[ZIP_DRV_ALG_BITMAP_IDX].cap_val;

	if ((alg & cap_val) == alg)

		return true;
@@ -507,10 +527,8 @@ static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm) 
	}



	/* let's open all compression/decompression cores */

	dcomp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

				       ZIP_DECOMP_ENABLE_BITMAP, qm->cap_ver);

	comp_bm = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

				      ZIP_COMP_ENABLE_BITMAP, qm->cap_ver);

	dcomp_bm = zip_cap_reg_record[ZIP_DECOMP_ENABLE_BITMAP_IDX].cap_val;

	comp_bm = zip_cap_reg_record[ZIP_COMP_ENABLE_BITMAP_IDX].cap_val;

	writel(HZIP_DECOMP_CHECK_ENABLE | dcomp_bm | comp_bm, base + HZIP_CLOCK_GATE_CTRL);



	/* enable sqc,cqc writeback */
@@ -737,9 +755,8 @@ static int hisi_zip_core_debug_init(struct hisi_qm *qm) 
	char buf[HZIP_BUF_SIZE];

	int i;



	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);

	zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,

						qm->cap_ver);

	zip_core_num = zip_cap_reg_record[ZIP_CORE_NUM_CAP_IDX].cap_val;

	zip_comp_core_num = zip_cap_reg_record[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;



	for (i = 0; i < zip_core_num; i++) {

		if (i < zip_comp_core_num)
@@ -881,7 +898,7 @@ static int hisi_zip_show_last_regs_init(struct hisi_qm *qm) 
	u32 zip_core_num;

	int i, j, idx;



	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);

	zip_core_num = zip_cap_reg_record[ZIP_CORE_NUM_CAP_IDX].cap_val;



	debug->last_words = kcalloc(core_dfx_regs_num * zip_core_num + com_dfx_regs_num,

				    sizeof(unsigned int), GFP_KERNEL);
@@ -937,9 +954,9 @@ static void hisi_zip_show_last_dfx_regs(struct hisi_qm *qm) 
				 hzip_com_dfx_regs[i].name, debug->last_words[i], val);

	}



	zip_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CORE_NUM_CAP, qm->cap_ver);

	zip_comp_core_num = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_CLUSTER_COMP_NUM_CAP,

						qm->cap_ver);

	zip_core_num = zip_cap_reg_record[ZIP_CORE_NUM_CAP_IDX].cap_val;

	zip_comp_core_num = zip_cap_reg_record[ZIP_CLUSTER_COMP_NUM_CAP_IDX].cap_val;



	for (i = 0; i < zip_core_num; i++) {

		if (i < zip_comp_core_num)

			scnprintf(buf, sizeof(buf), "Comp_core-%d", i);
@@ -1091,6 +1108,17 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hisi_zip) 
	return ret;

}



static void zip_pre_store_cap_reg(struct hisi_qm *qm)

{

	int i, size;



	size = ARRAY_SIZE(zip_cap_reg_record);

	for (i = 0; i < size; i++) {

		zip_cap_reg_record[i].cap_val = hisi_qm_get_hw_info(qm, zip_basic_cap_info,

						zip_cap_reg_record[i].type, qm->cap_ver);

	}

}



static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

{

	u64 alg_msk;
@@ -1129,7 +1157,10 @@ static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		return ret;

	}



	alg_msk = hisi_qm_get_hw_info(qm, zip_basic_cap_info, ZIP_DEV_ALG_BITMAP, qm->cap_ver);

	/* Fetch and save the value of capability registers */

	zip_pre_store_cap_reg(qm);



	alg_msk = zip_cap_reg_record[ZIP_DEV_ALG_BITMAP_IDX].cap_val;

	ret = hisi_qm_set_algs(qm, alg_msk, zip_dev_algs, ARRAY_SIZE(zip_dev_algs));

	if (ret) {

		pci_err(qm->pdev, "Failed to set zip algs!\n");