Commit c54b39a5 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'drm-intel-next-2022-04-13-1' of... 

Merge tag 'drm-intel-next-2022-04-13-1' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

drm/i915 feature pull for v5.19:

Features and functionality:
- Add support for new Tile 4 format on DG2 (Stan)
- Add support for new CCS clear color compression on DG2 (Mika, Juha-Pekka)
- Add support for new render and media compression formats on DG2 (Matt)
- Support multiple eDP and LVDS native mode refresh rates (Ville)
- Support static DRRS (Ville)
- ATS-M platform info (Matt)
- RPL-S PCI IDs (Tejas)
- Extend DP HDR support to HSW+ (Uma)
- Bump ADL-P DMC version to v2.16 (Madhumitha)
- Let users disable PSR2 while enabling PSR1 (José)

Refactoring and cleanups:
- Massive DRRS and panel fixed mode refactoring and cleanups (Ville)
- Power well refactoring and cleanup (Imre)
- Clean up and refactor crtc readout and compute config (Ville)
- Use kernel string helpers (Lucas)
- Refactor gmbus pin lookups and allocation (Jani)
- PCH display cleanups (Ville)
- DPLL and DPLL manager refactoring (Ville)
- Include and header refactoring (Jani, Tvrtko)
- DMC abstractions (Jani)
- Non-x86 build refactoring (Casey)
- VBT parsing refactoring (Ville)
- Bigjoiner refactoring (Ville)
- Optimize plane, pfit, scaler, etc. programming using unlocked writes (Ville)
- Split several register writes in commit to noarm+arm pairs (Ville)
- Clean up SAGV handling (Ville)
- Clean up bandwidth and ddb allocation (Ville)
- FBC cleanups (Ville)

Fixes:
- Fix native HDMI and DP HDMI DFP clock limits on deep color/4:2:0 (Ville)
- Fix DMC firmware platform check (Lucas)
- Fix cursor coordinates on bigjoiner secondary (Ville)
- Fix MSO vs. bigjoiner timing confusion (Ville)
- Fix ADL-P eDP voltage swing (José)
- Fix VRR capability property update (Manasi)
- Log DG2 SNPS PHY calibration errors (Matt, Lucas)
- Fix PCODE request status checks (Stan)
- Fix uncore unclaimed access warnings (Lucas)
- Fix VBT new max TMDS clock parsing (Shawn)
- Fix ADL-P non-existent underrun recovery (Swathi Dhanavanthri)
- Fix ADL-N stepping info (Tejas)
- Fix DPT mapping flags to contiguous (Stan)
- Fix DG2 max display bandwidth (Vinod)
- Fix DP low voltage SKU checks (Ankit)
- Fix RPL-S VT-d translation enable via quirk (Tejas)
- Fixes to PSR2 (José)
- Fix PIPE_MBUS_DBOX_CTL programming (José)
- Fix LTTPR capability read/check on DP 1.2 (Imre)
- Fix ADL-P register corruption after DDI clock enabling (Imre)
- Fix ADL-P MBUS DBOX BW and B credits (Caz)

Merges:
- Backmerge drm-next (Rodrigo, Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/874k2xgewe.fsf@intel.com
parents b85ffe47 b39d2c62

Documentation/gpu/i915.rst

+1 −13
Original line number Diff line number Diff line
@@ -187,19 +187,7 @@ Display Refresh Rate Switching (DRRS) 
   :doc: Display Refresh Rate Switching (DRRS)



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_enable



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_disable



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_invalidate



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_flush



.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c

   :functions: intel_drrs_init

   :internal:



DPIO

----

arch/x86/kernel/early-quirks.c

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/bcma/bcma_regs.h>

#include <linux/platform_data/x86/apple.h>

#include <drm/i915_drm.h>

#include <drm/i915_pciids.h>

#include <asm/pci-direct.h>

#include <asm/dma.h>

#include <asm/io_apic.h>

drivers/gpu/drm/dp/drm_dp.c

+36 −22
Original line number Diff line number Diff line
@@ -2390,9 +2390,36 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S 
}

EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);



static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,

				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,

				  u8 *buf, int buf_size)

{

	/*

	 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns

	 * corrupted values when reading from the 0xF0000- range with a block

	 * size bigger than 1.

	 */

	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;

	int offset;

	int ret;



	for (offset = 0; offset < buf_size; offset += block_size) {

		ret = drm_dp_dpcd_read(aux,

				       address + offset,

				       &buf[offset], block_size);

		if (ret < 0)

			return ret;



		WARN_ON(ret != block_size);

	}



	return 0;

}



/**

 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities

 * @aux: DisplayPort AUX channel

 * @dpcd: DisplayPort configuration data

 * @caps: buffer to return the capability info in

 *

 * Read capabilities common to all LTTPRs.
@@ -2400,25 +2427,19 @@ EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 
 * Returns 0 on success or a negative error code on failure.

 */

int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,

				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE])

{

	int ret;



	ret = drm_dp_dpcd_read(aux,

	return drm_dp_read_lttpr_regs(aux, dpcd,

				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,

				      caps, DP_LTTPR_COMMON_CAP_SIZE);

	if (ret < 0)

		return ret;



	WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);



	return 0;

}

EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);



/**

 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY

 * @aux: DisplayPort AUX channel

 * @dpcd: DisplayPort configuration data

 * @dp_phy: LTTPR PHY to read the capabilities for

 * @caps: buffer to return the capability info in

 *
@@ -2427,20 +2448,13 @@ EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 
 * Returns 0 on success or a negative error code on failure.

 */

int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,

			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			       enum drm_dp_phy dp_phy,

			       u8 caps[DP_LTTPR_PHY_CAP_SIZE])

{

	int ret;



	ret = drm_dp_dpcd_read(aux,

	return drm_dp_read_lttpr_regs(aux, dpcd,

				      DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),

				      caps, DP_LTTPR_PHY_CAP_SIZE);

	if (ret < 0)

		return ret;



	WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);



	return 0;

}

EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ i915-y += \ 
	display/intel_cursor.o \

	display/intel_display.o \

	display/intel_display_power.o \

	display/intel_display_power_well.o \

	display/intel_dmc.o \

	display/intel_dpio_phy.o \

	display/intel_dpll.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+23 −50
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
 * DisplayPort support for G4x,ILK,SNB,IVB,VLV,CHV (HSW+ handled by the DDI code).

 */



#include <linux/string_helpers.h>



#include "g4x_dp.h"

#include "intel_audio.h"

#include "intel_backlight.h"
@@ -22,58 +24,37 @@ 
#include "intel_pps.h"

#include "vlv_sideband.h"



struct dp_link_dpll {

	int clock;

	struct dpll dpll;

static const struct dpll g4x_dpll[] = {

	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },

	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },

};



static const struct dp_link_dpll g4x_dpll[] = {

	{ 162000,

		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },

	{ 270000,

		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }

static const struct dpll pch_dpll[] = {

	{ .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },

	{ .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },

};



static const struct dp_link_dpll pch_dpll[] = {

	{ 162000,

		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },

	{ 270000,

		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }

static const struct dpll vlv_dpll[] = {

	{ .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },

	{ .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },

};



static const struct dp_link_dpll vlv_dpll[] = {

	{ 162000,

		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },

	{ 270000,

		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }

};



/*

 * CHV supports eDP 1.4 that have  more link rates.

 * Below only provides the fixed rate but exclude variable rate.

 */

static const struct dp_link_dpll chv_dpll[] = {

	/*

	 * CHV requires to program fractional division for m2.

	 * m2 is stored in fixed point format using formula below

	 * (m2_int << 22) | m2_fraction

	 */

	{ 162000,	/* m2_int = 32, m2_fraction = 1677722 */

		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },

	{ 270000,	/* m2_int = 27, m2_fraction = 0 */

		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },

static const struct dpll chv_dpll[] = {

	/* m2 is .22 binary fixed point  */

	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },

	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },

};



const struct dpll *vlv_get_dpll(struct drm_i915_private *i915)

{

	return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll;

	return IS_CHERRYVIEW(i915) ? &chv_dpll[0] : &vlv_dpll[0];

}



void g4x_dp_set_clock(struct intel_encoder *encoder,

		      struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	const struct dp_link_dpll *divisor = NULL;

	const struct dpll *divisor = NULL;

	int i, count = 0;



	if (IS_G4X(dev_priv)) {
@@ -92,8 +73,8 @@ void g4x_dp_set_clock(struct intel_encoder *encoder, 


	if (divisor && count) {

		for (i = 0; i < count; i++) {

			if (pipe_config->port_clock == divisor[i].clock) {

				pipe_config->dpll = divisor[i].dpll;

			if (pipe_config->port_clock == divisor[i].dot) {

				pipe_config->dpll = divisor[i];

				pipe_config->clock_set = true;

				break;

			}
@@ -192,7 +173,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) 
	I915_STATE_WARN(cur_state != state,

			"[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",

			dig_port->base.base.base.id, dig_port->base.base.name,

			onoff(state), onoff(cur_state));

			str_on_off(state), str_on_off(cur_state));

}

#define assert_dp_port_disabled(d) assert_dp_port((d), false)
@@ -202,7 +183,7 @@ static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 


	I915_STATE_WARN(cur_state != state,

			"eDP PLL state assertion failure (expected %s, current %s)\n",

			onoff(state), onoff(cur_state));

			str_on_off(state), str_on_off(cur_state));

}

#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)

#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
@@ -514,9 +495,7 @@ static void intel_disable_dp(struct intel_atomic_state *state, 


	intel_dp->link_trained = false;



	if (old_crtc_state->has_audio)

		intel_audio_codec_disable(encoder,

					  old_crtc_state, old_conn_state);

	intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);



	/*

	 * Make sure the panel is off before trying to change the mode.
@@ -677,9 +656,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, 
{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);

	enum pipe pipe = crtc->pipe;

	intel_wakeref_t wakeref;



	if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
@@ -713,12 +690,8 @@ static void intel_enable_dp(struct intel_atomic_state *state, 
	intel_dp_start_link_train(intel_dp, pipe_config);

	intel_dp_stop_link_train(intel_dp, pipe_config);



	if (pipe_config->has_audio) {

		drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",

			pipe_name(pipe));

	intel_audio_codec_enable(encoder, pipe_config, conn_state);

}

}



static void g4x_enable_dp(struct intel_atomic_state *state,

			  struct intel_encoder *encoder,