Commit c54a6fe4 authored by Sung Lee's avatar Sung Lee Committed by Alex Deucher
Browse files

drm/amd/display: Revert dram_clock_change_latency for DCN2.1 



[WHY & HOW]
Using values provided by DF for latency may cause hangs in
multi display configurations. Revert change to previous value.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarSung Lee <sung.lee@amd.com>
Reviewed-by: default avatarHaonan Wang <Haonan.Wang2@amd.com>
Acked-by: default avatarEryk Brol <eryk.brol@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 04841b93

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -296,7 +296,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = { 
	.num_banks = 8,

	.num_chans = 4,

	.vmm_page_size_bytes = 4096,

	.dram_clock_change_latency_us = 11.72,

	.dram_clock_change_latency_us = 23.84,

	.return_bus_width_bytes = 64,

	.dispclk_dppclk_vco_speed_mhz = 3600,

	.xfc_bus_transport_time_us = 4,