Commit c54a0a7d authored by Tang Jinyang's avatar Tang Jinyang Committed by guzitao
Browse files

sw64: c3b: get MCLK rate dynamically according to specification 

Sunway inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8CCMP



--------------------------------

This patch allows OS to obtain maintence clock frequency from
specified memory location for a C3B based board. If it returns
0, fallback to default rate which is 25Mhz.

Signed-off-by: default avatarTang Jinyang <tangjinyang@wxiat.com>
Reviewed-by: default avatarHe Sheng <hesheng@wxiat.com>
Signed-off-by: default avatarGu Zitao <guzitao@wxiat.com>
parent d2bdb31c

drivers/clocksource/timer-sw64.c

+9 −2
Original line number Diff line number Diff line
@@ -122,13 +122,20 @@ static struct clocksource clocksource_tc = { 
};

#endif /* SMP */



#define DEFAULT_MCLK	25	/* Mhz */



void __init sw64_setup_clocksource(void)

{

	unsigned int mclk = *((unsigned char *)__va(0x908001));



	if (!mclk)

		mclk = DEFAULT_MCLK;



#ifdef CONFIG_SMP

	if (is_in_host())

		clocksource_register_khz(&clocksource_longtime, 25000);

		clocksource_register_khz(&clocksource_longtime, mclk * 1000);

	else

		clocksource_register_khz(&clocksource_vtime, 25000);

		clocksource_register_khz(&clocksource_vtime, DEFAULT_MCLK * 1000);

#else

	clocksource_register_hz(&clocksource_tc, get_cpu_freq());

	pr_info("Setup clocksource TC, mult = %d\n", clocksource_tc.mult);