Commit c535b6a1 authored by Yinghai Lu's avatar Yinghai Lu Committed by Ingo Molnar
Browse files

x86: let 32bit use apic_ops too 



Signed-off-by: default avatarYinghai Lu <yhlu.kernel@gmail.com>
Cc: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent af9d1388

arch/x86/kernel/apic_32.c

+31 −8
Original line number Diff line number Diff line
@@ -145,19 +145,13 @@ static int modern_apic(void) 
	return lapic_get_version() >= 0x14;

}



void apic_icr_write(u32 low, u32 id)

{

	apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(id));

	apic_write_around(APIC_ICR, low);

}



void apic_wait_icr_idle(void)

void xapic_wait_icr_idle(void)

{

	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)

		cpu_relax();

}



u32 safe_apic_wait_icr_idle(void)

u32 safe_xapic_wait_icr_idle(void)

{

	u32 send_status;

	int timeout;
@@ -173,6 +167,35 @@ u32 safe_apic_wait_icr_idle(void) 
	return send_status;

}



void xapic_icr_write(u32 low, u32 id)

{

	apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(id));

	apic_write_around(APIC_ICR, low);

}



u64 xapic_icr_read(void)

{

	u32 icr1, icr2;



	icr2 = apic_read(APIC_ICR2);

	icr1 = apic_read(APIC_ICR);



	return icr1 | ((u64)icr2 << 32);

}



static struct apic_ops xapic_ops = {

	.read = native_apic_mem_read,

	.write = native_apic_mem_write,

	.write_atomic = native_apic_mem_write_atomic,

	.icr_read = xapic_icr_read,

	.icr_write = xapic_icr_write,

	.wait_icr_idle = xapic_wait_icr_idle,

	.safe_wait_icr_idle = safe_xapic_wait_icr_idle,

};



struct apic_ops __read_mostly *apic_ops = &xapic_ops;

EXPORT_SYMBOL_GPL(apic_ops);



/**

 * enable_NMI_through_LVT0 - enable NMI through local vector table 0

 */

include/asm-x86/apic.h

+2 −11
Original line number Diff line number Diff line
@@ -49,11 +49,6 @@ extern int disable_apic; 
#ifdef CONFIG_PARAVIRT

#include <asm/paravirt.h>

#else

#ifndef CONFIG_X86_64

#define apic_write native_apic_mem_write

#define apic_write_atomic native_apic_mem_write_atomic

#define apic_read native_apic_mem_read

#endif

#define setup_boot_clock setup_boot_APIC_clock

#define setup_secondary_clock setup_secondary_APIC_clock

#endif
@@ -95,16 +90,13 @@ static inline u32 native_apic_msr_read(u32 reg) 
	return low;

}



#ifdef CONFIG_X86_32

extern void apic_wait_icr_idle(void);

extern u32 safe_apic_wait_icr_idle(void);

extern void apic_icr_write(u32 low, u32 id);

#else

#ifndef CONFIG_X86_32

extern int x2apic, x2apic_preenabled;

extern void check_x2apic(void);

extern void enable_x2apic(void);

extern void enable_IR_x2apic(void);

extern void x2apic_icr_write(u32 low, u32 id);

#endif



struct apic_ops {

	u32 (*read)(u32 reg);
@@ -125,7 +117,6 @@ extern struct apic_ops *apic_ops; 
#define apic_icr_write (apic_ops->icr_write)

#define apic_wait_icr_idle (apic_ops->wait_icr_idle)

#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)

#endif



extern int get_physical_broadcast(void);