Commit c52c90db authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Vinod Koul
Browse files

dt-bindings: phy: mediatek: tphy: add support hardware version 3 



The PHYA architecture is updated, and doesn't support slew rate
calibration anymore on 7nm or advanced process, add a new version
number to support it.
Due to the FreqMeter bank is not used but reserved, it's backward
with v2 until now.
For mt8195, no function changes when use generic v2 or v3 compatible,
but prefer to use v3's compatible, it will not waste the time to
calibrate the slew rate, and also correspond with hardware version.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1627028562-23584-1-git-send-email-chunfeng.yun@mediatek.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 07e97f74

Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

+9 −5
Original line number Original line Diff line number Diff line
@@ -15,7 +15,7 @@ description: | 
  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.

  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.





  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and

  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and

  T-PHY V2 (mt2712) when works on USB mode:

  T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:

  -----------------------------------

  -----------------------------------

  Version 1:

  Version 1:

  port        offset    bank

  port        offset    bank
@@ -34,7 +34,7 @@ description: | 
  u2 port2    0x1800    U2PHY_COM

  u2 port2    0x1800    U2PHY_COM

              ...

              ...





  Version 2:

  Version 2/3:

  port        offset    bank

  port        offset    bank

  u2 port0    0x0000    MISC

  u2 port0    0x0000    MISC

              0x0100    FMREG

              0x0100    FMREG
@@ -59,7 +59,8 @@ description: | 




  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back

  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back

  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are

  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are

  added on V2.

  added on V2; the FMREG bank for slew rate calibration is not used anymore

  and reserved on V3;





properties:

properties:

  $nodename:

  $nodename:
@@ -79,8 +80,11 @@ properties: 
              - mediatek,mt2712-tphy

              - mediatek,mt2712-tphy

              - mediatek,mt7629-tphy

              - mediatek,mt7629-tphy

              - mediatek,mt8183-tphy

              - mediatek,mt8183-tphy

              - mediatek,mt8195-tphy

          - const: mediatek,generic-tphy-v2

          - const: mediatek,generic-tphy-v2

      - items:

          - enum:

              - mediatek,mt8195-tphy

          - const: mediatek,generic-tphy-v3

      - const: mediatek,mt2701-u3phy

      - const: mediatek,mt2701-u3phy

        deprecated: true

        deprecated: true

      - const: mediatek,mt2712-u3phy

      - const: mediatek,mt2712-u3phy
@@ -91,7 +95,7 @@ properties: 
    description:

    description:

      Register shared by multiple ports, exclude port's private register.

      Register shared by multiple ports, exclude port's private register.

      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for

      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for

      T-PHY V2, such as mt2712.

      T-PHY V2/V3, such as mt2712.

    maxItems: 1

    maxItems: 1





  "#address-cells":

  "#address-cells":