Unverified Commit c5094f37 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
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riscv: dts: microchip: refactor icicle kit device tree 



Assorted minor changes to the MPFS/Icicle kit device tree:

- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 72560c65

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

+20 −17
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2020 Microchip Technology Inc */

/* Copyright (c) 2020-2021 Microchip Technology Inc */



/dts-v1/;
@@ -13,11 +13,11 @@ 
	compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";



	aliases {

		ethernet0 = &emac1;

		serial0 = &serial0;

		serial1 = &serial1;

		serial2 = &serial2;

		serial3 = &serial3;

		ethernet0 = &mac1;

		serial0 = &mmuart0;

		serial1 = &mmuart1;

		serial2 = &mmuart2;

		serial3 = &mmuart3;

	};



	chosen {
@@ -39,19 +39,19 @@ 
	clock-frequency = <600000000>;

};



&serial0 {

&mmuart0 {

	status = "okay";

};



&serial1 {

&mmuart1 {

	status = "okay";

};



&serial2 {

&mmuart2 {

	status = "okay";

};



&serial3 {

&mmuart3 {

	status = "okay";

};
@@ -61,7 +61,10 @@ 
	bus-width = <4>;

	disable-wp;

	cap-sd-highspeed;

	cap-mmc-highspeed;

	card-detect-delay = <200>;

	mmc-ddr-1_8v;

	mmc-hs200-1_8v;

	sd-uhs-sdr12;

	sd-uhs-sdr25;

	sd-uhs-sdr50;
@@ -72,22 +75,22 @@ 
	status = "okay";

};



&emac0 {

&mac0 {

	phy-mode = "sgmii";

	phy-handle = <&phy0>;

	phy0: ethernet-phy@8 {

		reg = <8>;

		ti,fifo-depth = <0x01>;

	};

};



&emac1 {

&mac1 {

	status = "okay";

	phy-mode = "sgmii";

	phy-handle = <&phy1>;

	phy1: ethernet-phy@9 {

		reg = <9>;

		ti,fifo-depth = <0x01>;

		ti,fifo-depth = <0x1>;

	};

	phy0: ethernet-phy@8 {

		reg = <8>;

		ti,fifo-depth = <0x1>;

	};

};

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

+32 −33
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/* Copyright (c) 2020 Microchip Technology Inc */

/* Copyright (c) 2020-2021 Microchip Technology Inc */



/dts-v1/;

#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -15,7 +15,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		cpu@0 {

		cpu0: cpu@0 {

			compatible = "sifive,e51", "sifive,rocket0", "riscv";

			device_type = "cpu";

			i-cache-block-size = <64>;
@@ -33,7 +33,7 @@ 
			};

		};



		cpu@1 {

		cpu1: cpu@1 {

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;
@@ -60,7 +60,7 @@ 
			};

		};



		cpu@2 {

		cpu2: cpu@2 {

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;
@@ -87,7 +87,7 @@ 
			};

		};



		cpu@3 {

		cpu3: cpu@3 {

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;
@@ -114,7 +114,7 @@ 
			};

		};



		cpu@4 {

		cpu4: cpu@4 {

			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";

			d-cache-block-size = <64>;

			d-cache-sets = <64>;
@@ -152,8 +152,9 @@ 
		compatible = "simple-bus";

		ranges;



		cache-controller@2010000 {

		cctrllr: cache-controller@2010000 {

			compatible = "sifive,fu540-c000-ccache", "cache";

			reg = <0x0 0x2010000 0x0 0x1000>;

			cache-block-size = <64>;

			cache-level = <2>;

			cache-sets = <1024>;
@@ -161,10 +162,9 @@ 
			cache-unified;

			interrupt-parent = <&plic>;

			interrupts = <1>, <2>, <3>;

			reg = <0x0 0x2010000 0x0 0x1000>;

		};



		clint@2000000 {

		clint: clint@2000000 {

			compatible = "sifive,fu540-c000-clint", "sifive,clint0";

			reg = <0x0 0x2000000 0x0 0xC000>;

			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
@@ -174,6 +174,15 @@ 
					      <&cpu4_intc 3>, <&cpu4_intc 7>;

		};



		dma@3000000 {

			compatible = "sifive,fu540-c000-pdma";

			reg = <0x0 0x3000000 0x0 0x8000>;

			interrupt-parent = <&plic>;

			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,

				     <30>;

			#dma-cells = <1>;

		};



		plic: interrupt-controller@c000000 {

			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";

			reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -188,15 +197,6 @@ 
			riscv,ndev = <186>;

		};



		dma@3000000 {

			compatible = "sifive,fu540-c000-pdma";

			reg = <0x0 0x3000000 0x0 0x8000>;

			interrupt-parent = <&plic>;

			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,

				     <30>;

			#dma-cells = <1>;

		};



		clkcfg: clkcfg@20002000 {

			compatible = "microchip,mpfs-clkcfg";

			reg = <0x0 0x20002000 0x0 0x1000>;
@@ -204,7 +204,7 @@ 
			#clock-cells = <1>;

		};



		serial0: serial@20000000 {

		mmuart0: serial@20000000 {

			compatible = "ns16550a";

			reg = <0x0 0x20000000 0x0 0x400>;

			reg-io-width = <4>;
@@ -216,7 +216,7 @@ 
			status = "disabled";

		};



		serial1: serial@20100000 {

		mmuart1: serial@20100000 {

			compatible = "ns16550a";

			reg = <0x0 0x20100000 0x0 0x400>;

			reg-io-width = <4>;
@@ -228,7 +228,7 @@ 
			status = "disabled";

		};



		serial2: serial@20102000 {

		mmuart2: serial@20102000 {

			compatible = "ns16550a";

			reg = <0x0 0x20102000 0x0 0x400>;

			reg-io-width = <4>;
@@ -240,7 +240,7 @@ 
			status = "disabled";

		};



		serial3: serial@20104000 {

		mmuart3: serial@20104000 {

			compatible = "ns16550a";

			reg = <0x0 0x20104000 0x0 0x400>;

			reg-io-width = <4>;
@@ -257,37 +257,36 @@ 
			compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";

			reg = <0x0 0x20008000 0x0 0x1000>;

			interrupt-parent = <&plic>;

			interrupts = <88>, <89>;

			interrupts = <88>;

			clocks = <&clkcfg CLK_MMC>;

			max-frequency = <200000000>;

			status = "disabled";

		};



		emac0: ethernet@20110000 {

		mac0: ethernet@20110000 {

			compatible = "cdns,macb";

			reg = <0x0 0x20110000 0x0 0x2000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupt-parent = <&plic>;

			interrupts = <64>, <65>, <66>, <67>;

			interrupts = <64>, <65>, <66>, <67>, <68>, <69>;

			local-mac-address = [00 00 00 00 00 00];

			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;

			clock-names = "pclk", "hclk";

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <0>;

		};



		emac1: ethernet@20112000 {

		mac1: ethernet@20112000 {

			compatible = "cdns,macb";

			reg = <0x0 0x20112000 0x0 0x2000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupt-parent = <&plic>;

			interrupts = <70>, <71>, <72>, <73>;

			interrupts = <70>, <71>, <72>, <73>, <74>, <75>;

			local-mac-address = [00 00 00 00 00 00];

			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;

			status = "disabled";

			clock-names = "pclk", "hclk";

			#address-cells = <1>;

			#size-cells = <0>;

			status = "disabled";

		};



	};

};