Commit c4f98fd6 authored by D Scott Phillips's avatar D Scott Phillips Committed by Wen Zhiwei
Browse files

arm64: errata: Enable the AC03_CPU_38 workaround for ampere1a

stable inclusion
from stable-v6.6.54
commit 0e6774ec012bf8bf28eac2a00478d7e0639a3a8f
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAZ3K2

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=0e6774ec012bf8bf28eac2a00478d7e0639a3a8f



--------------------------------

commit db0d8a84348b876df7c4276f0cbce5df3b769f5f upstream.

The ampere1a cpu is affected by erratum AC04_CPU_10 which is the same
bug as AC03_CPU_38. Add ampere1a to the AC03_CPU_38 workaround midr list.

Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarD Scott Phillips <scott@os.amperecomputing.com>
Acked-by: default avatarOliver Upton <oliver.upton@linux.dev>
Link: https://lore.kernel.org/r/20240827211701.2216719-1-scott@os.amperecomputing.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Conflicts:
 Documentation/arch/arm64/silicon-errata.rst
 arch/arm64/Kconfig
 arch/arm64/include/asm/cputype.h
 arch/arm64/kernel/cpu_errata.c
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent 3f7973aa
Loading
Loading
Loading
Loading
+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Ampere         | AmpereOne       | AC03_CPU_38     | AMPERE_ERRATUM_AC03_CPU_38  |
+----------------+-----------------+-----------------+-----------------------------+
| Ampere         | AmpereOne AC04  | AC04_CPU_10     | AMPERE_ERRATUM_AC03_CPU_38  |
+----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
| ARM            | Cortex-A510     | #2457168        | ARM64_ERRATUM_2457168       |
+----------------+-----------------+-----------------+-----------------------------+
+1 −1
Original line number Diff line number Diff line
@@ -427,7 +427,7 @@ config AMPERE_ERRATUM_AC03_CPU_38
	default y
	help
	  This option adds an alternative code sequence to work around Ampere
	  erratum AC03_CPU_38 on AmpereOne.
          errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.

	  The affected design reports FEAT_HAFDBS as not implemented in
	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
+2 −0
Original line number Diff line number Diff line
@@ -152,6 +152,7 @@
#define APPLE_CPU_PART_M2_AVALANCHE_MAX	0x039

#define AMPERE_CPU_PART_AMPERE1		0xAC3
#define AMPERE_CPU_PART_AMPERE1A       0xAC4

#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */

@@ -229,6 +230,7 @@
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
#define MIDR_AMPERE1A MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1A)
#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)

/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
+9 −1
Original line number Diff line number Diff line
@@ -526,6 +526,14 @@ static const struct midr_range erratum_spec_unpriv_load_list[] = {
};
#endif

#ifdef CONFIG_AMPERE_ERRATUM_AC03_CPU_38
static const struct midr_range erratum_ac03_cpu_38_list[] = {
       MIDR_ALL_VERSIONS(MIDR_AMPERE1),
       MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
       {},
};
#endif

const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
	{
@@ -852,7 +860,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
	{
		.desc = "AmpereOne erratum AC03_CPU_38",
		.capability = ARM64_WORKAROUND_AMPERE_AC03_CPU_38,
		ERRATA_MIDR_ALL_VERSIONS(MIDR_AMPERE1),
		ERRATA_MIDR_RANGE_LIST(erratum_ac03_cpu_38_list),
	},
#endif
#ifdef CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH