Commit c4f7ac64 authored by Kashyap Desai's avatar Kashyap Desai Committed by Martin K. Petersen
Browse files

scsi: mpi3mr: Add mpi30 Rev-R headers and Kconfig 

This adds the Kconfig and mpi30 headers.

Link: https://lore.kernel.org/r/20210520152545.2710479-2-kashyap.desai@broadcom.com


Cc: sathya.prakash@broadcom.com
Cc: bvanassche@acm.org
Cc: hch@infradead.org
Reviewed-by: default avatarHannes Reinecke <hare@suse.de>
Reviewed-by: default avatarTomas Henzl <thenzl@redhat.com>
Reviewed-by: default avatarHimanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: default avatarKashyap Desai <kashyap.desai@broadcom.com>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent f6b41429

drivers/scsi/Kconfig

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@@ -482,6 +482,7 @@ config SCSI_ARCMSR 
source "drivers/scsi/esas2r/Kconfig"

source "drivers/scsi/megaraid/Kconfig.megaraid"

source "drivers/scsi/mpt3sas/Kconfig"

source "drivers/scsi/mpi3mr/Kconfig"

source "drivers/scsi/smartpqi/Kconfig"

source "drivers/scsi/ufs/Kconfig"

drivers/scsi/Makefile

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@@ -99,6 +99,7 @@ obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o 
obj-$(CONFIG_MEGARAID_NEWGEN)	+= megaraid/

obj-$(CONFIG_MEGARAID_SAS)	+= megaraid/

obj-$(CONFIG_SCSI_MPT3SAS)	+= mpt3sas/

obj-$(CONFIG_SCSI_MPI3MR)	+= mpi3mr/

obj-$(CONFIG_SCSI_UFSHCD)	+= ufs/

obj-$(CONFIG_SCSI_ACARD)	+= atp870u.o

obj-$(CONFIG_SCSI_SUNESP)	+= esp_scsi.o	sun_esp.o

drivers/scsi/mpi3mr/Kconfig

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# SPDX-License-Identifier: GPL-2.0-or-later



config SCSI_MPI3MR

	tristate "Broadcom MPI3 Storage Controller Device Driver"

	depends on PCI && SCSI

	help

	MPI3 based Storage & RAID Controllers Driver.

drivers/scsi/mpi3mr/mpi/mpi30_image.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *  Copyright 2018-2021 Broadcom Inc. All rights reserved.

 *

 */

#ifndef MPI30_IMAGE_H

#define MPI30_IMAGE_H     1

struct mpi3_comp_image_version {

	__le16     build_num;

	__le16     customer_id;

	u8         phase_minor;

	u8         phase_major;

	u8         gen_minor;

	u8         gen_major;

};



struct mpi3_hash_exclusion_format {

	__le32                     offset;

	__le32                     size;

};



#define MPI3_IMAGE_HASH_EXCUSION_NUM                           (4)

struct mpi3_component_image_header {

	__le32                            signature0;

	__le32                            load_address;

	__le32                            data_size;

	__le32                            start_offset;

	__le32                            signature1;

	__le32                            flash_offset;

	__le32                            image_size;

	__le32                            version_string_offset;

	__le32                            build_date_string_offset;

	__le32                            build_time_string_offset;

	__le32                            environment_variable_offset;

	__le32                            application_specific;

	__le32                            signature2;

	__le32                            header_size;

	__le32                            crc;

	__le32                            flags;

	__le32                            secondary_flash_offset;

	__le32                            etp_offset;

	__le32                            etp_size;

	union mpi3_version_union             rmc_interface_version;

	union mpi3_version_union             etp_interface_version;

	struct mpi3_comp_image_version        component_image_version;

	struct mpi3_hash_exclusion_format     hash_exclusion[MPI3_IMAGE_HASH_EXCUSION_NUM];

	__le32                            next_image_header_offset;

	union mpi3_version_union             security_version;

	__le32                            reserved84[31];

};



#define MPI3_IMAGE_HEADER_SIGNATURE0_MPI3                     (0xeb00003e)

#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_INVALID                (0x00000000)

#define MPI3_IMAGE_HEADER_SIGNATURE1_APPLICATION              (0x20505041)

#define MPI3_IMAGE_HEADER_SIGNATURE1_FIRST_MUTABLE            (0x20434d46)

#define MPI3_IMAGE_HEADER_SIGNATURE1_BSP                      (0x20505342)

#define MPI3_IMAGE_HEADER_SIGNATURE1_ROM_BIOS                 (0x534f4942)

#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_X64                  (0x4d494948)

#define MPI3_IMAGE_HEADER_SIGNATURE1_HII_ARM                  (0x41494948)

#define MPI3_IMAGE_HEADER_SIGNATURE1_CPLD                     (0x444c5043)

#define MPI3_IMAGE_HEADER_SIGNATURE1_SPD                      (0x20445053)

#define MPI3_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE                (0x20534147)

#define MPI3_IMAGE_HEADER_SIGNATURE1_PBLP                     (0x504c4250)

#define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE                    (0x50584546)

#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK         (0x00000030)

#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI          (0x00000000)

#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI           (0x00000010)

#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA                 (0x00000008)

#define MPI3_IMAGE_HEADER_FLAGS_REQUIRES_ACTIVATION           (0x00000004)

#define MPI3_IMAGE_HEADER_FLAGS_COMPRESSED                    (0x00000002)

#define MPI3_IMAGE_HEADER_FLAGS_FLASH                         (0x00000001)

#define MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET                   (0x00)

#define MPI3_IMAGE_HEADER_LOAD_ADDRESS_OFFSET                 (0x04)

#define MPI3_IMAGE_HEADER_DATA_SIZE_OFFSET                    (0x08)

#define MPI3_IMAGE_HEADER_START_OFFSET_OFFSET                 (0x0c)

#define MPI3_IMAGE_HEADER_SIGNATURE1_OFFSET                   (0x10)

#define MPI3_IMAGE_HEADER_FLASH_OFFSET_OFFSET                 (0x14)

#define MPI3_IMAGE_HEADER_FLASH_SIZE_OFFSET                   (0x18)

#define MPI3_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET        (0x1c)

#define MPI3_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET     (0x20)

#define MPI3_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET            (0x24)

#define MPI3_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET        (0x28)

#define MPI3_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET         (0x2c)

#define MPI3_IMAGE_HEADER_SIGNATURE2_OFFSET                   (0x30)

#define MPI3_IMAGE_HEADER_HEADER_SIZE_OFFSET                  (0x34)

#define MPI3_IMAGE_HEADER_CRC_OFFSET                          (0x38)

#define MPI3_IMAGE_HEADER_FLAGS_OFFSET                        (0x3c)

#define MPI3_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET       (0x40)

#define MPI3_IMAGE_HEADER_ETP_OFFSET_OFFSET                   (0x44)

#define MPI3_IMAGE_HEADER_ETP_SIZE_OFFSET                     (0x48)

#define MPI3_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET            (0x4c)

#define MPI3_IMAGE_HEADER_ETP_INTERFACE_VER_OFFSET            (0x50)

#define MPI3_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET          (0x54)

#define MPI3_IMAGE_HEADER_HASH_EXCLUSION_OFFSET               (0x5c)

#define MPI3_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET     (0x7c)

#define MPI3_IMAGE_HEADER_SIZE                                (0x100)

struct mpi3_extended_image_header {

	u8                                image_type;

	u8                                reserved01[3];

	__le32                            checksum;

	__le32                            image_size;

	__le32                            next_image_header_offset;

	__le32                            reserved10[4];

	__le32                            identify_string[8];

};



#define MPI3_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)

#define MPI3_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)

#define MPI3_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0c)

#define MPI3_EXT_IMAGE_HEADER_SIZE              (0x40)

#define MPI3_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)

#define MPI3_EXT_IMAGE_TYPE_NVDATA                  (0x03)

#define MPI3_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)

#define MPI3_EXT_IMAGE_TYPE_ENCRYPTED_HASH          (0x09)

#define MPI3_EXT_IMAGE_TYPE_RDE                     (0x0a)

#define MPI3_EXT_IMAGE_TYPE_AUXILIARY_PROCESSOR     (0x0b)

#define MPI3_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)

#define MPI3_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xff)

struct mpi3_supported_device {

	__le16                     device_id;

	__le16                     vendor_id;

	__le16                     device_id_mask;

	__le16                     reserved06;

	u8                         low_pci_rev;

	u8                         high_pci_rev;

	__le16                     reserved0a;

	__le32                     reserved0c;

};



#ifndef MPI3_SUPPORTED_DEVICE_MAX

#define MPI3_SUPPORTED_DEVICE_MAX                      (1)

#endif

struct mpi3_supported_devices_data {

	u8                         image_version;

	u8                         reserved01;

	u8                         num_devices;

	u8                         reserved03;

	__le32                     reserved04;

	struct mpi3_supported_device   supported_device[MPI3_SUPPORTED_DEVICE_MAX];

};



#ifndef MPI3_ENCRYPTED_HASH_MAX

#define MPI3_ENCRYPTED_HASH_MAX                      (1)

#endif

struct mpi3_encrypted_hash_entry {

	u8                         hash_image_type;

	u8                         hash_algorithm;

	u8                         encryption_algorithm;

	u8                         reserved03;

	__le32                     reserved04;

	__le32                     encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];

};



#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE      (0x03)

#define MPI3_HASH_ALGORITHM_VERSION_MASK             (0xe0)

#define MPI3_HASH_ALGORITHM_VERSION_NONE             (0x00)

#define MPI3_HASH_ALGORITHM_VERSION_SHA1             (0x20)

#define MPI3_HASH_ALGORITHM_VERSION_SHA2             (0x40)

#define MPI3_HASH_ALGORITHM_VERSION_SHA3             (0x60)

#define MPI3_HASH_ALGORITHM_SIZE_MASK                (0x1f)

#define MPI3_HASH_ALGORITHM_SIZE_UNUSED              (0x00)

#define MPI3_HASH_ALGORITHM_SIZE_SHA256              (0x01)

#define MPI3_HASH_ALGORITHM_SIZE_SHA512              (0x02)

#define MPI3_ENCRYPTION_ALGORITHM_UNUSED             (0x00)

#define MPI3_ENCRYPTION_ALGORITHM_RSA256             (0x01)

#define MPI3_ENCRYPTION_ALGORITHM_RSA512             (0x02)

#define MPI3_ENCRYPTION_ALGORITHM_RSA1024            (0x03)

#define MPI3_ENCRYPTION_ALGORITHM_RSA2048            (0x04)

#define MPI3_ENCRYPTION_ALGORITHM_RSA4096            (0x05)

#define MPI3_ENCRYPTION_ALGORITHM_RSA3072            (0x06)

#ifndef MPI3_PUBLIC_KEY_MAX

#define MPI3_PUBLIC_KEY_MAX                          (1)

#endif

struct mpi3_encrypted_key_with_hash_entry {

	u8                         hash_image_type;

	u8                         hash_algorithm;

	u8                         encryption_algorithm;

	u8                         reserved03;

	__le32                     reserved04;

	__le32                     public_key[MPI3_PUBLIC_KEY_MAX];

	__le32                     encrypted_hash[MPI3_ENCRYPTED_HASH_MAX];

};



#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX

#define MPI3_ENCRYPTED_HASH_ENTRY_MAX               (1)

#endif

struct mpi3_encrypted_hash_data {

	u8                                  image_version;

	u8                                  num_hash;

	__le16                              reserved02;

	__le32                              reserved04;

	struct mpi3_encrypted_hash_entry        encrypted_hash_entry[MPI3_ENCRYPTED_HASH_ENTRY_MAX];

};



#ifndef MPI3_AUX_PROC_DATA_MAX

#define MPI3_AUX_PROC_DATA_MAX               (1)

#endif

struct mpi3_aux_processor_data {

	u8                         boot_method;

	u8                         num_load_addr;

	u8                         reserved02;

	u8                         type;

	__le32                     version;

	__le32                     load_address[8];

	__le32                     reserved28[22];

	__le32                     aux_processor_data[MPI3_AUX_PROC_DATA_MAX];

};



#define MPI3_AUX_PROC_DATA_OFFSET                                     (0x80)

#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_MSG                          (0x00)

#define MPI3_AUXPROCESSOR_BOOT_METHOD_MO_DOORBELL                     (0x01)

#define MPI3_AUXPROCESSOR_BOOT_METHOD_COMPONENT                       (0x02)

#define MPI3_AUXPROCESSOR_TYPE_ARM_A15                                (0x00)

#define MPI3_AUXPROCESSOR_TYPE_ARM_M0                                 (0x01)

#define MPI3_AUXPROCESSOR_TYPE_ARM_R4                                 (0x02)

#endif

drivers/scsi/mpi3mr/mpi/mpi30_init.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */

/*

 *  Copyright 2016-2021 Broadcom Inc. All rights reserved.

 *

 */

#ifndef MPI30_INIT_H

#define MPI30_INIT_H     1

struct mpi3_scsi_io_cdb_eedp32 {

	u8                 cdb[20];

	__be32          primary_reference_tag;

	__le16             primary_application_tag;

	__le16             primary_application_tag_mask;

	__le32             transfer_length;

};



union mpi3_scso_io_cdb_union {

	u8                         cdb32[32];

	struct mpi3_scsi_io_cdb_eedp32 eedp32;

	struct mpi3_sge_common         sge;

};



struct mpi3_scsi_io_request {

	__le16                     host_tag;

	u8                         ioc_use_only02;

	u8                         function;

	__le16                     ioc_use_only04;

	u8                         ioc_use_only06;

	u8                         msg_flags;

	__le16                     change_count;

	__le16                     dev_handle;

	__le32                     flags;

	__le32                     skip_count;

	__le32                     data_length;

	u8                         lun[8];

	union mpi3_scso_io_cdb_union  cdb;

	union mpi3_sge_union          sgl[4];

};



#define MPI3_SCSIIO_MSGFLAGS_METASGL_VALID                  (0x80)

#define MPI3_SCSIIO_FLAGS_LARGE_CDB                         (0x60000000)

#define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS                    (0x00000000)

#define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16               (0x20000000)

#define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER            (0x40000000)

#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK                (0x07000000)

#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ             (0x00000000)

#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ             (0x01000000)

#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ            (0x02000000)

#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ACAQ                (0x04000000)

#define MPI3_SCSIIO_FLAGS_CMDPRI_MASK                       (0x00f00000)

#define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT                      (20)

#define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK                (0x000c0000)

#define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER    (0x00000000)

#define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE               (0x00040000)

#define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ                (0x00080000)

#define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK                 (0x00030000)

#define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI              (0x00010000)

#define MPI3_SCSIIO_METASGL_INDEX                           (3)

struct mpi3_scsi_io_reply {

	__le16                     host_tag;

	u8                         ioc_use_only02;

	u8                         function;

	__le16                     ioc_use_only04;

	u8                         ioc_use_only06;

	u8                         msg_flags;

	__le16                     ioc_use_only08;

	__le16                     ioc_status;

	__le32                     ioc_log_info;

	u8                         scsi_status;

	u8                         scsi_state;

	__le16                     dev_handle;

	__le32                     transfer_count;

	__le32                     sense_count;

	__le32                     response_data;

	__le16                     task_tag;

	__le16                     scsi_status_qualifier;

	__le32                     eedp_error_offset;

	__le16                     eedp_observed_app_tag;

	__le16                     eedp_observed_guard;

	__le32                     eedp_observed_ref_tag;

	__le64                     sense_data_buffer_address;

};



#define MPI3_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID        (0x01)

#define MPI3_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID        (0x02)

#define MPI3_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID         (0x04)

#define MPI3_SCSI_STATUS_GOOD                   (0x00)

#define MPI3_SCSI_STATUS_CHECK_CONDITION        (0x02)

#define MPI3_SCSI_STATUS_CONDITION_MET          (0x04)

#define MPI3_SCSI_STATUS_BUSY                   (0x08)

#define MPI3_SCSI_STATUS_INTERMEDIATE           (0x10)

#define MPI3_SCSI_STATUS_INTERMEDIATE_CONDMET   (0x14)

#define MPI3_SCSI_STATUS_RESERVATION_CONFLICT   (0x18)

#define MPI3_SCSI_STATUS_COMMAND_TERMINATED     (0x22)

#define MPI3_SCSI_STATUS_TASK_SET_FULL          (0x28)

#define MPI3_SCSI_STATUS_ACA_ACTIVE             (0x30)

#define MPI3_SCSI_STATUS_TASK_ABORTED           (0x40)

#define MPI3_SCSI_STATE_SENSE_MASK              (0x03)

#define MPI3_SCSI_STATE_SENSE_VALID             (0x00)

#define MPI3_SCSI_STATE_SENSE_FAILED            (0x01)

#define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY      (0x02)

#define MPI3_SCSI_STATE_SENSE_NOT_AVAILABLE     (0x03)

#define MPI3_SCSI_STATE_NO_SCSI_STATUS          (0x04)

#define MPI3_SCSI_STATE_TERMINATED              (0x08)

#define MPI3_SCSI_STATE_RESPONSE_DATA_VALID     (0x10)

#define MPI3_SCSI_RSP_RESPONSECODE_MASK         (0x000000ff)

#define MPI3_SCSI_RSP_RESPONSECODE_SHIFT        (0)

#define MPI3_SCSI_RSP_ARI2_MASK                 (0x0000ff00)

#define MPI3_SCSI_RSP_ARI2_SHIFT                (8)

#define MPI3_SCSI_RSP_ARI1_MASK                 (0x00ff0000)

#define MPI3_SCSI_RSP_ARI1_SHIFT                (16)

#define MPI3_SCSI_RSP_ARI0_MASK                 (0xff000000)

#define MPI3_SCSI_RSP_ARI0_SHIFT                (24)

#define MPI3_SCSI_TASKTAG_UNKNOWN               (0xffff)

struct mpi3_scsi_task_mgmt_request {

	__le16                     host_tag;

	u8                         ioc_use_only02;

	u8                         function;

	__le16                     ioc_use_only04;

	u8                         ioc_use_only06;

	u8                         msg_flags;

	__le16                     change_count;

	__le16                     dev_handle;

	__le16                     task_host_tag;

	u8                         task_type;

	u8                         reserved0f;

	__le16                     task_request_queue_id;

	__le16                     reserved12;

	__le32                     reserved14;

	u8                         lun[8];

};



#define MPI3_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU      (0x08)

#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK               (0x01)

#define MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK_SET           (0x02)

#define MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET             (0x03)

#define MPI3_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET       (0x05)

#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET           (0x06)

#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK               (0x07)

#define MPI3_SCSITASKMGMT_TASKTYPE_CLEAR_ACA                (0x08)

#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_TASK_SET           (0x09)

#define MPI3_SCSITASKMGMT_TASKTYPE_QUERY_ASYNC_EVENT        (0x0a)

#define MPI3_SCSITASKMGMT_TASKTYPE_I_T_NEXUS_RESET          (0x0b)

struct mpi3_scsi_task_mgmt_reply {

	__le16                     host_tag;

	u8                         ioc_use_only02;

	u8                         function;

	__le16                     ioc_use_only04;

	u8                         ioc_use_only06;

	u8                         msg_flags;

	__le16                     ioc_use_only08;

	__le16                     ioc_status;

	__le32                     ioc_log_info;

	__le32                     termination_count;

	__le32                     response_data;

	__le32                     reserved18;

};



#define MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC      (0x80)

#endif