Commit c4f71901 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvmarm-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD 

KVM/arm64 updates for Linux 5.13

New features:

- Stage-2 isolation for the host kernel when running in protected mode
- Guest SVE support when running in nVHE mode
- Force W^X hypervisor mappings in nVHE mode
- ITS save/restore for guests using direct injection with GICv4.1
- nVHE panics now produce readable backtraces
- Guest support for PTP using the ptp_kvm driver
- Performance improvements in the S2 fault handler
- Alexandru is now a reviewer (not really a new feature...)

Fixes:
- Proper emulation of the GICR_TYPER register
- Handle the complete set of relocation in the nVHE EL2 object
- Get rid of the oprofile dependency in the PMU code (and of the
  oprofile body parts at the same time)
- Debug and SPE fixes
- Fix vcpu reset
parents fd49e8ee 9a8aae60

Documentation/ABI/testing/sysfs-bus-coresight-devices-trbe

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What:		/sys/bus/coresight/devices/trbe<cpu>/align

Date:		March 2021

KernelVersion:	5.13

Contact:	Anshuman Khandual <anshuman.khandual@arm.com>

Description:	(Read) Shows the TRBE write pointer alignment. This value

		is fetched from the TRBIDR register.



What:		/sys/bus/coresight/devices/trbe<cpu>/flag

Date:		March 2021

KernelVersion:	5.13

Contact:	Anshuman Khandual <anshuman.khandual@arm.com>

Description:	(Read) Shows if TRBE updates in the memory are with access

		and dirty flag updates as well. This value is fetched from

		the TRBIDR register.

Documentation/admin-guide/kernel-parameters.txt

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@@ -2279,8 +2279,7 @@ 
				   state is kept private from the host.

				   Not valid if the kernel is running in EL2.



			Defaults to VHE/nVHE based on hardware support and

			the value of CONFIG_ARM64_VHE.

			Defaults to VHE/nVHE based on hardware support.



	kvm-arm.vgic_v3_group0_trap=

			[KVM,ARM] Trap guest accesses to GICv3 group-0

Documentation/devicetree/bindings/arm/ete.yaml

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

# Copyright 2021, Arm Ltd

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/ete.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: ARM Embedded Trace Extensions



maintainers:

  - Suzuki K Poulose <suzuki.poulose@arm.com>

  - Mathieu Poirier <mathieu.poirier@linaro.org>



description: |

  Arm Embedded Trace Extension(ETE) is a per CPU trace component that

  allows tracing the CPU execution. It overlaps with the CoreSight ETMv4

  architecture and has extended support for future architecture changes.

  The trace generated by the ETE could be stored via legacy CoreSight

  components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer

  Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to

  legacy CoreSight components, a node must be listed per instance, along

  with any optional connection graph as per the coresight bindings.

  See bindings/arm/coresight.txt.



properties:

  $nodename:

    pattern: "^ete([0-9a-f]+)$"

  compatible:

    items:

      - const: arm,embedded-trace-extension



  cpu:

    description: |

      Handle to the cpu this ETE is bound to.

    $ref: /schemas/types.yaml#/definitions/phandle



  out-ports:

    description: |

      Output connections from the ETE to legacy CoreSight trace bus.

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port:

        description: Output connection from the ETE to legacy CoreSight Trace bus.

        $ref: /schemas/graph.yaml#/properties/port



required:

  - compatible

  - cpu



additionalProperties: false



examples:



# An ETE node without legacy CoreSight connections

  - |

    ete0 {

      compatible = "arm,embedded-trace-extension";

      cpu = <&cpu_0>;

    };

# An ETE node with legacy CoreSight connections

  - |

   ete1 {

      compatible = "arm,embedded-trace-extension";

      cpu = <&cpu_1>;



      out-ports {        /* legacy coresight connection */

         port {

             ete1_out_port: endpoint {

                remote-endpoint = <&funnel_in_port0>;

             };

         };

      };

   };



...

Documentation/devicetree/bindings/arm/trbe.yaml

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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

# Copyright 2021, Arm Ltd

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/trbe.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: ARM Trace Buffer Extensions



maintainers:

  - Anshuman Khandual <anshuman.khandual@arm.com>



description: |

  Arm Trace Buffer Extension (TRBE) is a per CPU component

  for storing trace generated on the CPU to memory. It is

  accessed via CPU system registers. The software can verify

  if it is permitted to use the component by checking the

  TRBIDR register.



properties:

  $nodename:

    const: "trbe"

  compatible:

    items:

      - const: arm,trace-buffer-extension



  interrupts:

    description: |

       Exactly 1 PPI must be listed. For heterogeneous systems where

       TRBE is only supported on a subset of the CPUs, please consult

       the arm,gic-v3 binding for details on describing a PPI partition.

    maxItems: 1



required:

  - compatible

  - interrupts



additionalProperties: false



examples:



  - |

   #include <dt-bindings/interrupt-controller/arm-gic.h>



   trbe {

     compatible = "arm,trace-buffer-extension";

     interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

   };

...

Documentation/trace/coresight/coresight-trbe.rst

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.. SPDX-License-Identifier: GPL-2.0



==============================

Trace Buffer Extension (TRBE).

==============================



    :Author:   Anshuman Khandual <anshuman.khandual@arm.com>

    :Date:     November 2020



Hardware Description

--------------------



Trace Buffer Extension (TRBE) is a percpu hardware which captures in system

memory, CPU traces generated from a corresponding percpu tracing unit. This

gets plugged in as a coresight sink device because the corresponding trace

generators (ETE), are plugged in as source device.



The TRBE is not compliant to CoreSight architecture specifications, but is

driven via the CoreSight driver framework to support the ETE (which is

CoreSight compliant) integration.



Sysfs files and directories

---------------------------



The TRBE devices appear on the existing coresight bus alongside the other

coresight devices::



	>$ ls /sys/bus/coresight/devices

	trbe0  trbe1  trbe2 trbe3



The ``trbe<N>`` named TRBEs are associated with a CPU.::



	>$ ls /sys/bus/coresight/devices/trbe0/

        align flag



*Key file items are:-*

   * ``align``: TRBE write pointer alignment

   * ``flag``: TRBE updates memory with access and dirty flags