Commit c4f486f1 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Russell King (Oracle)
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ARM: 9198/1: spectre-bhb: simplify BPIALL vector macro 



The BPIALL mitigation for Spectre-BHB adds a single instruction to the
handler sequence that doesn't clobber any registers. Given that these
sequences are 10 instructions long, they don't fit neatly into a
cacheline anyway, so we can simply move that single instruction to the
start of the unmitigated one, and rearrange the symbol names accordingly.

Signed-off-by: default avatarArd Biesheuvel <ardb@kernel.org>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
parent 50807460

arch/arm/kernel/entry-armv.S

+6 −15
Original line number Diff line number Diff line
@@ -1078,6 +1078,12 @@ __kuser_helper_end: 
 */

	.macro	vector_stub, name, mode, correction=0

	.align	5

#ifdef CONFIG_HARDEN_BRANCH_HISTORY

vector_bhb_bpiall_\name:

	mcr	p15, 0, r0, c7, c5, 6	@ BPIALL

	@ isb not needed due to "movs pc, lr" in the vector stub

	@ which gives a "context synchronisation".

#endif



vector_\name:

	.if \correction
@@ -1129,21 +1135,6 @@ vector_bhb_loop8_\name: 
	isb

	b	2b

ENDPROC(vector_bhb_loop8_\name)



vector_bhb_bpiall_\name:

	.if \correction

	sub	lr, lr, #\correction

	.endif



	@ Save r0, lr_<exception> (parent PC)

	stmia	sp, {r0, lr}



	@ bhb workaround

	mcr	p15, 0, r0, c7, c5, 6	@ BPIALL

	@ isb not needed due to "movs pc, lr" in the vector stub

	@ which gives a "context synchronisation".

	b	2b

ENDPROC(vector_bhb_bpiall_\name)

	.previous

#endif