Commit c4e40c01 authored by Alim Akhtar's avatar Alim Akhtar Committed by Krzysztof Kozlowski
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arm64: dts: exynos: Add cpu cache information to Exynos7 



Add CPU caches information to its dt nodes so that the same is available
to userspace via sysfs.  This SoC has 48/32 KB I/D cache
for each cores and 2MB of L2 cache.

Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20210622130551.67446-1-alim.akhtar@samsung.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
parent e73f0f0e

arch/arm64/boot/dts/exynos/exynos7.dtsi

+35 −0
Original line number Diff line number Diff line
@@ -54,6 +54,13 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x0>;

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&atlas_l2>;

		};



		cpu_atlas1: cpu@1 {
@@ -61,6 +68,13 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x1>;

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&atlas_l2>;

		};



		cpu_atlas2: cpu@2 {
@@ -68,6 +82,13 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x2>;

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&atlas_l2>;

		};



		cpu_atlas3: cpu@3 {
@@ -75,6 +96,20 @@ 
			compatible = "arm,cortex-a57";

			reg = <0x3>;

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&atlas_l2>;

		};



		atlas_l2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};

	};