Commit c4dfad81 authored by YuBiao Wang's avatar YuBiao Wang Committed by Alex Deucher
Browse files

drm/amdgpu: dequeue mes scheduler during fini 



[Why]
If mes is not dequeued during fini, mes will be in an uncleaned state
during reload, then mes couldn't receive some commands which leads to
reload failure.

[How]
Perform MES dequeue via MMIO after all the unmap jobs are done by mes
and before kiq fini.

v2: Move the dequeue operation inside kiq_hw_fini.

Signed-off-by: default avatarYuBiao Wang <YuBiao.Wang@amd.com>
Reviewed-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c520ba3f

drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

+39 −3
Original line number Diff line number Diff line
@@ -1156,6 +1156,42 @@ static int mes_v11_0_sw_fini(void *handle) 
	return 0;

}



static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev)

{

	uint32_t data;

	int i;



	mutex_lock(&adev->srbm_mutex);

	soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0);



	/* disable the queue if it's active */

	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {

		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);

		for (i = 0; i < adev->usec_timeout; i++) {

			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))

				break;

			udelay(1);

		}

	}

	data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);

	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

				DOORBELL_EN, 0);

	data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL,

				DOORBELL_HIT, 1);

	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data);



	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0);



	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0);

	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0);

	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0);



	soc21_grbm_select(adev, 0, 0, 0, 0);

	mutex_unlock(&adev->srbm_mutex);



	adev->mes.ring.sched.ready = false;

}



static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring)

{

	uint32_t tmp;
@@ -1207,6 +1243,9 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 


static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)

{

	if (adev->mes.ring.sched.ready)

		mes_v11_0_kiq_dequeue_sched(adev);



	mes_v11_0_enable(adev, false);

	return 0;

}
@@ -1262,9 +1301,6 @@ static int mes_v11_0_hw_init(void *handle) 


static int mes_v11_0_hw_fini(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	adev->mes.ring.sched.ready = false;

	return 0;

}