Unverified Commit c4d39282 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-dt64-5.15-1' of... 

Merge tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/dt

mvebu dt64 for 5.15 (part 1)

 - DTS updates for Marvell Armada CN913x platforms

   + Add support for Armada CN913x Development Board topology "B"
   + Add support for Armada CN913x Reference Design boards (CRB)
   + Fixes the NAND partitioning scheme in DTS eliminating gap between
     consecutive partitions
   + Fix 10Gb ports PHY mode names

 - Extend PCIe MEM space on Armada 37xx: useful for some combination
    of PCIe cards where the initial 16MB was not enough

* tag 'mvebu-dt64-5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: armada-37xx: Extend PCIe MEM space
  arch/arm64: dts: change 10gbase-kr to 10gbase-r in Armada
  arm64: dts: add support for Marvell cn9130-crb platform
  dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boards
  arm64: dts: cn913x: add device trees for topology B boards

Link: https://lore.kernel.org/r/878s10ypxe.fsf@BL-laptop


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 911f0faf 514ef1e6

arch/arm64/boot/dts/marvell/Makefile

+5 −0
Original line number Diff line number Diff line
@@ -16,5 +16,10 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb 
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-puzzle-m801.dtb

dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db-B.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db-B.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb

dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb

arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts

+17 −0
Original line number Diff line number Diff line
@@ -132,6 +132,23 @@ 
	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;

	status = "okay";

	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;

	/*

	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property

	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and

	 * 2 size cells and also expects that the second range starts at 16 MB offset. If these

	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address

	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window

	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.

	 * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in

	 * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix):

	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7

	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf

	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33

	 */

	#address-cells = <3>;

	#size-cells = <2>;

	ranges = <0x81000000 0 0xe8000000   0 0xe8000000   0 0x01000000   /* Port 0 IO */

		  0x82000000 0 0xe9000000   0 0xe9000000   0 0x07000000>; /* Port 0 MEM */



	/* enabled by U-Boot if PCIe module is present */

	status = "disabled";

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -489,8 +489,15 @@ 
			#interrupt-cells = <1>;

			msi-parent = <&pcie0>;

			msi-controller;

			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */

				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/

			/*

			 * The 128 MiB address range [0xe8000000-0xf0000000] is

			 * dedicated for PCIe and can be assigned to 8 windows

			 * with size a power of two. Use one 64 KiB window for

			 * IO at the end and the remaining seven windows

			 * (totaling 127 MiB) for MEM.

			 */

			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */

				  0x81000000 0 0xefff0000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0 0 0 1 &pcie_intc 0>,

					<0 0 0 2 &pcie_intc 1>,

arch/arm64/boot/dts/marvell/armada-7040-db.dts

+1 −1
Original line number Diff line number Diff line
@@ -282,7 +282,7 @@ 
&cp0_eth0 {

	status = "okay";

	/* Network PHY */

	phy-mode = "10gbase-kr";

	phy-mode = "10gbase-r";

	/* Generic PHY, providing serdes lanes */

	phys = <&cp0_comphy2 0>;

arch/arm64/boot/dts/marvell/armada-8040-db.dts

+2 −2
Original line number Diff line number Diff line
@@ -195,7 +195,7 @@ 


&cp0_eth0 {

	status = "okay";

	phy-mode = "10gbase-kr";

	phy-mode = "10gbase-r";



	fixed-link {

		speed = <10000>;
@@ -348,7 +348,7 @@ 


&cp1_eth0 {

	status = "okay";

	phy-mode = "10gbase-kr";

	phy-mode = "10gbase-r";



	fixed-link {

		speed = <10000>;