Commit c4c75188 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/kms/nv50-: use NVIDIA's headers for core head_mode() 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent fb3939e2

drivers/gpu/drm/nouveau/dispnv50/head507d.c

+41 −10
Original line number Original line Diff line number Diff line
@@ -318,16 +318,47 @@ head507d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 13)))

	if ((ret = PUSH_WAIT(push, 13)))

		return ret;

		return ret;





	PUSH_NVSQ(push, NV507D, 0x0804 + (i * 0x400), 0x00800000 | m->clock,

	PUSH_MTHD(push, NV507D, HEAD_SET_PIXEL_CLOCK(i),

				0x0808 + (i * 0x400), m->interlace ? 0x00000002 : 0x00000000);

		  NVVAL(NV507D, HEAD_SET_PIXEL_CLOCK, FREQUENCY, m->clock) |

	PUSH_NVSQ(push, NV507D, 0x0810 + (i * 0x400), 0x00000000,

		  NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, MODE, CLK_CUSTOM) |

				0x0814 + (i * 0x400), m->v.active  << 16 | m->h.active,

		  NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, ADJ1000DIV1001, FALSE) |

				0x0818 + (i * 0x400), m->v.synce   << 16 | m->h.synce,

		  NVDEF(NV507D, HEAD_SET_PIXEL_CLOCK, NOT_DRIVER, FALSE),

				0x081c + (i * 0x400), m->v.blanke  << 16 | m->h.blanke,



				0x0820 + (i * 0x400), m->v.blanks  << 16 | m->h.blanks,

				HEAD_SET_CONTROL(i),

				0x0824 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s,

		  NVVAL(NV507D, HEAD_SET_CONTROL, STRUCTURE, m->interlace));

				0x0828 + (i * 0x400), asyh->mode.v.blankus);



	PUSH_NVSQ(push, NV507D, 0x082c + (i * 0x400), 0x00000000);

	PUSH_MTHD(push, NV507D, HEAD_SET_OVERSCAN_COLOR(i),

		  NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |

		  NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |

		  NVVAL(NV507D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),



				HEAD_SET_RASTER_SIZE(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |

		  NVVAL(NV507D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),



				HEAD_SET_RASTER_SYNC_END(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |

		  NVVAL(NV507D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),



				HEAD_SET_RASTER_BLANK_END(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |

		  NVVAL(NV507D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),



				HEAD_SET_RASTER_BLANK_START(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |

		  NVVAL(NV507D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),



				HEAD_SET_RASTER_VERT_BLANK2(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |

		  NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e),



				HEAD_SET_RASTER_VERT_BLANK_DMI(i),

		  NVVAL(NV507D, HEAD_SET_RASTER_VERT_BLANK_DMI, DURATION, m->v.blankus));



	PUSH_MTHD(push, NV507D, HEAD_SET_DEFAULT_BASE_COLOR(i),

		  NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |

		  NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |

		  NVVAL(NV507D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0));

	return 0;

	return 0;

}

}

drivers/gpu/drm/nouveau/dispnv50/head907d.c

+49 −11
Original line number Original line Diff line number Diff line
@@ -280,17 +280,55 @@ head907d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 
	if ((ret = PUSH_WAIT(push, 14)))

	if ((ret = PUSH_WAIT(push, 14)))

		return ret;

		return ret;





	PUSH_NVSQ(push, NV907D, 0x0410 + (i * 0x300), 0x00000000,

	PUSH_MTHD(push, NV907D, HEAD_SET_OVERSCAN_COLOR(i),

				0x0414 + (i * 0x300), m->v.active  << 16 | m->h.active,

		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, RED, 0) |

				0x0418 + (i * 0x300), m->v.synce   << 16 | m->h.synce,

		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, GRN, 0) |

				0x041c + (i * 0x300), m->v.blanke  << 16 | m->h.blanke,

		  NVVAL(NV907D, HEAD_SET_OVERSCAN_COLOR, BLU, 0),

				0x0420 + (i * 0x300), m->v.blanks  << 16 | m->h.blanks,



				0x0424 + (i * 0x300), m->v.blank2e << 16 | m->v.blank2s);

				HEAD_SET_RASTER_SIZE(i),

	PUSH_NVSQ(push, NV907D, 0x042c + (i * 0x300), 0x00000000,

		  NVVAL(NV907D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |

				0x0430 + (i * 0x300), 0xffffff00);

		  NVVAL(NV907D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),

	PUSH_NVSQ(push, NV907D, 0x0450 + (i * 0x300), m->clock * 1000,



				0x0454 + (i * 0x300), 0x00200000,

				HEAD_SET_RASTER_SYNC_END(i),

				0x0458 + (i * 0x300), m->clock * 1000);

		  NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |

		  NVVAL(NV907D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),



				HEAD_SET_RASTER_BLANK_END(i),

		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |

		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),



				HEAD_SET_RASTER_BLANK_START(i),

		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |

		  NVVAL(NV907D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks),



				HEAD_SET_RASTER_VERT_BLANK2(i),

		  NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YSTART, m->v.blank2s) |

		  NVVAL(NV907D, HEAD_SET_RASTER_VERT_BLANK2, YEND, m->v.blank2e));



	PUSH_MTHD(push, NV907D, HEAD_SET_DEFAULT_BASE_COLOR(i),

		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, RED, 0) |

		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, GREEN, 0) |

		  NVVAL(NV907D, HEAD_SET_DEFAULT_BASE_COLOR, BLUE, 0),



				HEAD_SET_CRC_CONTROL(i),

		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, CONTROLLING_CHANNEL, CORE) |

		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, EXPECT_BUFFER_COLLAPSE, FALSE) |

		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, TIMESTAMP_MODE, FALSE) |

		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, PRIMARY_OUTPUT, NONE) |

		  NVDEF(NV907D, HEAD_SET_CRC_CONTROL, SECONDARY_OUTPUT, NONE));



	PUSH_MTHD(push, NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),

		  NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000) |

		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, ADJ1000DIV1001, FALSE),



				HEAD_SET_PIXEL_CLOCK_CONFIGURATION(i),

		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, MODE, CLK_CUSTOM) |

		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, NOT_DRIVER, FALSE) |

		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_CONFIGURATION, ENABLE_HOPPING, FALSE),



				HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),

		  NVVAL(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000) |

		  NVDEF(NV907D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, ADJ1000DIV1001, FALSE));

	return 0;

	return 0;

}

}

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

+30 −10
Original line number Original line Diff line number Diff line
@@ -187,20 +187,40 @@ headc37d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 
	const int i = head->base.index;

	const int i = head->base.index;

	int ret;

	int ret;





	if ((ret = PUSH_WAIT(push, 13)))

	if ((ret = PUSH_WAIT(push, 15)))

		return ret;

		return ret;





	PUSH_NVSQ(push, NVC37D, 0x2064 + (i * 0x400), m->v.active  << 16 | m->h.active,

	PUSH_MTHD(push, NVC37D, HEAD_SET_RASTER_SIZE(i),

				0x2068 + (i * 0x400), m->v.synce   << 16 | m->h.synce,

		  NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |

				0x206c + (i * 0x400), m->v.blanke  << 16 | m->h.blanke,

		  NVVAL(NVC37D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),

				0x2070 + (i * 0x400), m->v.blanks  << 16 | m->h.blanks,



				0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);

				HEAD_SET_RASTER_SYNC_END(i),

	PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace,

		  NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |

				0x200c + (i * 0x400), m->clock * 1000);

		  NVVAL(NVC37D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),

	PUSH_NVSQ(push, NVC37D, 0x2028 + (i * 0x400), m->clock * 1000);



				HEAD_SET_RASTER_BLANK_END(i),

		  NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |

		  NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),



				HEAD_SET_RASTER_BLANK_START(i),

		  NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |

		  NVVAL(NVC37D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));



	//XXX:

	PUSH_NVSQ(push, NVC37D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);

	PUSH_NVSQ(push, NVC37D, 0x2008 + (i * 0x400), m->interlace);



	PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),

		  NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000));



	PUSH_MTHD(push, NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),

		  NVVAL(NVC37D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000));





	/*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */

	/*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */

	PUSH_NVSQ(push, NVC37D, 0x2030 + (i * 0x400), 0x00000124);

	PUSH_MTHD(push, NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS(i),

		  NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |

		  NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_LUT, USAGE_1025) |

		  NVDEF(NVC37D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));

	return 0;

	return 0;

}

}

drivers/gpu/drm/nouveau/dispnv50/headc57d.c

+33 −10
Original line number Original line Diff line number Diff line
@@ -25,6 +25,8 @@ 




#include <nvif/pushc37b.h>

#include <nvif/pushc37b.h>





#include <nvhw/class/clc57d.h>



static int

static int

headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh)

headc57d_or(struct nv50_head *head, struct nv50_head_atom *asyh)

{

{
@@ -183,20 +185,41 @@ headc57d_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 
	const int i = head->base.index;

	const int i = head->base.index;

	int ret;

	int ret;





	if ((ret = PUSH_WAIT(push, 13)))

	if ((ret = PUSH_WAIT(push, 15)))

		return ret;

		return ret;





	PUSH_NVSQ(push, NVC57D, 0x2064 + (i * 0x400), m->v.active  << 16 | m->h.active,

	PUSH_MTHD(push, NVC57D, HEAD_SET_RASTER_SIZE(i),

				0x2068 + (i * 0x400), m->v.synce   << 16 | m->h.synce,

		  NVVAL(NVC57D, HEAD_SET_RASTER_SIZE, WIDTH, m->h.active) |

				0x206c + (i * 0x400), m->v.blanke  << 16 | m->h.blanke,

		  NVVAL(NVC57D, HEAD_SET_RASTER_SIZE, HEIGHT, m->v.active),

				0x2070 + (i * 0x400), m->v.blanks  << 16 | m->h.blanks,



				0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);

				HEAD_SET_RASTER_SYNC_END(i),

	PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace,

		  NVVAL(NVC57D, HEAD_SET_RASTER_SYNC_END, X, m->h.synce) |

				0x200c + (i * 0x400), m->clock * 1000);

		  NVVAL(NVC57D, HEAD_SET_RASTER_SYNC_END, Y, m->v.synce),

	PUSH_NVSQ(push, NVC57D, 0x2028 + (i * 0x400), m->clock * 1000);



				HEAD_SET_RASTER_BLANK_END(i),

		  NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_END, X, m->h.blanke) |

		  NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_END, Y, m->v.blanke),



				HEAD_SET_RASTER_BLANK_START(i),

		  NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_START, X, m->h.blanks) |

		  NVVAL(NVC57D, HEAD_SET_RASTER_BLANK_START, Y, m->v.blanks));



	//XXX:

	PUSH_NVSQ(push, NVC57D, 0x2074 + (i * 0x400), m->v.blank2e << 16 | m->v.blank2s);

	PUSH_NVSQ(push, NVC57D, 0x2008 + (i * 0x400), m->interlace);



	PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY(i),

		  NVVAL(NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY, HERTZ, m->clock * 1000));



	PUSH_MTHD(push, NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(i),

		  NVVAL(NVC57D, HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX, HERTZ, m->clock * 1000));





	/*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */

	/*XXX: HEAD_USAGE_BOUNDS, doesn't belong here. */

	PUSH_NVSQ(push, NVC57D, 0x2030 + (i * 0x400), 0x00001114);

	PUSH_MTHD(push, NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS(i),

		  NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, CURSOR, USAGE_W256_H256) |

		  NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OLUT_ALLOWED, TRUE) |

		  NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, OUTPUT_SCALER_TAPS, TAPS_2) |

		  NVDEF(NVC57D, HEAD_SET_HEAD_USAGE_BOUNDS, UPSCALING_ALLOWED, TRUE));

	return 0;

	return 0;

}

}