Commit c4955d9c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2022-05-24' of... 

Merge tag 'drm-intel-next-fixes-2022-05-24' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

drm/i915 fixes for v5.19 merge window:
- Build, sparse, UB, and CFI fixes
- Variable scope fix
- Audio pipe logging fix
- ICL+ DSI NULL dereference fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87sfozuj44.fsf@intel.com
parents 03536823 0ea91781

drivers/gpu/drm/i915/display/intel_audio.c

+2 −2
Original line number Diff line number Diff line
@@ -827,7 +827,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, 
	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Enable audio codec on pipe %c, %u bytes ELD\n",

		    connector->base.id, connector->name,

		    encoder->base.base.id, encoder->base.name,

		    pipe, drm_eld_size(connector->eld));

		    pipe_name(pipe), drm_eld_size(connector->eld));



	/* FIXME precompute the ELD in .compute_config() */

	if (!connector->eld[0])
@@ -888,7 +888,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder, 


	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s][ENCODER:%d:%s] Disable audio codec on pipe %c\n",

		    connector->base.id, connector->name,

		    encoder->base.base.id, encoder->base.name, pipe);

		    encoder->base.base.id, encoder->base.name, pipe_name(pipe));



	if (dev_priv->audio.funcs)

		dev_priv->audio.funcs->audio_codec_disable(encoder,

drivers/gpu/drm/i915/display/intel_display_power.c

+4 −4
Original line number Diff line number Diff line
@@ -2428,7 +2428,7 @@ intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port) 
	if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_io == POWER_DOMAIN_INVALID)

		return POWER_DOMAIN_PORT_DDI_IO_A;



	return domains->ddi_io + port - domains->port_start;

	return domains->ddi_io + (int)(port - domains->port_start);

}



enum intel_display_power_domain
@@ -2439,7 +2439,7 @@ intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port po 
	if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_lanes == POWER_DOMAIN_INVALID)

		return POWER_DOMAIN_PORT_DDI_LANES_A;



	return domains->ddi_lanes + port - domains->port_start;

	return domains->ddi_lanes + (int)(port - domains->port_start);

}



static const struct intel_ddi_port_domains *
@@ -2465,7 +2465,7 @@ intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch 
	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)

		return POWER_DOMAIN_AUX_A;



	return domains->aux_legacy_usbc + aux_ch - domains->aux_ch_start;

	return domains->aux_legacy_usbc + (int)(aux_ch - domains->aux_ch_start);

}



enum intel_display_power_domain
@@ -2476,5 +2476,5 @@ intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch au 
	if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_tbt == POWER_DOMAIN_INVALID)

		return POWER_DOMAIN_AUX_TBT1;



	return domains->aux_tbt + aux_ch - domains->aux_ch_start;

	return domains->aux_tbt + (int)(aux_ch - domains->aux_ch_start);

}

drivers/gpu/drm/i915/display/intel_dsi_vbt.c

+22 −11
Original line number Diff line number Diff line
@@ -125,9 +125,25 @@ struct i2c_adapter_lookup { 
#define  ICL_GPIO_DDPA_CTRLCLK_2	8

#define  ICL_GPIO_DDPA_CTRLDATA_2	9



static enum port intel_dsi_seq_port_to_port(u8 port)

static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi,

					    u8 seq_port)

{

	return port ? PORT_C : PORT_A;

	/*

	 * If single link DSI is being used on any port, the VBT sequence block

	 * send packet apparently always has 0 for the port. Just use the port

	 * we have configured, and ignore the sequence block port.

	 */

	if (hweight8(intel_dsi->ports) == 1)

		return ffs(intel_dsi->ports) - 1;



	if (seq_port) {

		if (intel_dsi->ports & PORT_B)

			return PORT_B;

		else if (intel_dsi->ports & PORT_C)

			return PORT_C;

	}



	return PORT_A;

}



static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
@@ -149,15 +165,10 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 


	seq_port = (flags >> MIPI_PORT_SHIFT) & 3;



	/* For DSI single link on Port A & C, the seq_port value which is

	 * parsed from Sequence Block#53 of VBT has been set to 0

	 * Now, read/write of packets for the DSI single link on Port A and

	 * Port C will based on the DVO port from VBT block 2.

	 */

	if (intel_dsi->ports == (1 << PORT_C))

		port = PORT_C;

	else

		port = intel_dsi_seq_port_to_port(seq_port);

	port = intel_dsi_seq_port_to_port(intel_dsi, seq_port);



	if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))

		goto out;



	dsi_device = intel_dsi->dsi_hosts[port]->device;

	if (!dsi_device) {

drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c

+12 −11
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 
#include "intel_rc6.h"

#include "intel_rps.h"



#ifdef CONFIG_PM

enum intel_gt_sysfs_op {

	INTEL_GT_SYSFS_MIN = 0,

	INTEL_GT_SYSFS_MAX,
@@ -92,6 +91,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr, 
#define sysfs_gt_attribute_r_max_func(d, a, f) \

		sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)



#ifdef CONFIG_PM

static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)

{

	intel_wakeref_t wakeref;
@@ -457,22 +457,23 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *dev, 
}



#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \

	struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \

	struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)

	static struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \

	static struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)



#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name)				\

		INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)

#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name)				\

		INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)



static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);

static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);

/* The below macros generate static structures */

INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);

INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);



static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);

drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h

+1 −1
Original line number Diff line number Diff line
@@ -50,7 +50,7 @@ 


#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN		(GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ		GUC_HXG_REQUEST_MSG_0_DATA0

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffff << 16)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY		(0xffffU << 16)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN		(0xffff << 0)

#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32		GUC_HXG_REQUEST_MSG_n_DATAn

#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64		GUC_HXG_REQUEST_MSG_n_DATAn