Commit c457ac02 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Lorenzo Pieralisi
Browse files

PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS 

During L1SS, gate the Master clock supplied to the MHI bus to save power.

Link: https://lore.kernel.org/r/20220914075350.7992-7-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
parent 6dbba2b5

drivers/pci/controller/dwc/pcie-qcom-ep.c

+9 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#define PARF_SYS_CTRL				0x00

#define PARF_DB_CTRL				0x10

#define PARF_PM_CTRL				0x20

#define PARF_MHI_CLOCK_RESET_CTRL		0x174

#define PARF_MHI_BASE_ADDR_LOWER		0x178

#define PARF_MHI_BASE_ADDR_UPPER		0x17c

#define PARF_DEBUG_INT_EN			0x190
@@ -89,6 +90,9 @@ 
#define PARF_PM_CTRL_READY_ENTR_L23		BIT(2)

#define PARF_PM_CTRL_REQ_NOT_ENTR_L1		BIT(5)



/* PARF_MHI_CLOCK_RESET_CTRL fields */

#define PARF_MSTR_AXI_CLK_EN			BIT(1)



/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */

#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN	BIT(0)
@@ -394,6 +398,11 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) 
		       pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);

	writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);



	/* Gate Master AXI clock to MHI bus during L1SS */

	val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);

	val &= ~PARF_MSTR_AXI_CLK_EN;

	val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);



	dw_pcie_ep_init_notify(&pcie_ep->pci.ep);



	/* Enable LTSSM */