mfd: ti_am335x_tscadc: Reword the comment explaining the dividers

	pm_runtime_get_sync(&pdev->dev);

	/*

	 * The TSC_ADC_Subsystem has 2 clock domains

	 * OCP_CLK and ADC_CLK.

	 * The ADC clock is expected to run at target of 3MHz,

	 * and expected to capture 12-bit data at a rate of 200 KSPS.

	 * The TSC_ADC_SS controller design assumes the OCP clock is

	 * at least 6x faster than the ADC clock.

	 * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.

	 * ADCs produce a 12-bit sample every 15 ADC_CLK cycles.

	 * am33xx ADCs expect to capture 200ksps.

	 * We need the ADC clocks to run at 3MHz.

	 * This frequency is valid since TSC_ADC_SS controller design

	 * assumes the OCP clock is at least 6x faster than the ADC clock.

	 */

	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");

	if (IS_ERR(clk)) {